An Implementation of an Address Generator Using Hash Memories

An address generator produces a unique address from 1 to k for the input that matches to one of k registered vectors, and produces 0 for other inputs. This paper presents the super hybrid method to design an address generator. The hash memories realize about 96% of the registered vectors, while the reconfigurable PLA realizes the remaining 4% of the registered vectors. With the super hybrid method, we can implement up to 20 times more registered vectors than the conventional method that uses only logic elements of an FPGA. Experimental results using lists of English words show that the usefulness of the approach.

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