X-clock tree construction for antenna avoidance

The antenna effect is a phenomenon in the plasma-based nanometer processes that many charges are accumulated on metal wires which cause the degradation of gate-oxide. It also influences the chip reliability and manufacturing yield. Different with other methods based on Manhattan-architecture for the antenna avoidance, we propose the algorithm that combines jumper insertion and layer assignment (JILA) to eliminate antenna effects on X-architecture clock tree. Experimental results on benchmarks show that our algorithm can reduce all the antenna effects effectively by requiring just extra 20.7% in total vias on average, but the penalties in clock delay, skew, and power dissipation are controlled under the increments of 0.02%, 3.1%, and 0.02%, respectively.

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