On properties of algebraic transformations and the synthesis of multifault-irredundant circuits
暂无分享,去创建一个
[1] Zvi Kohavi,et al. Detection of Multiple Faults in Combinational Logic Networks , 1972, IEEE Transactions on Computers.
[2] R. Dandapani,et al. On the Design of Logic Networks with Redundancy and Testability Considerations , 1974, IEEE Transactions on Computers.
[3] Kurt Keutzer. Three competing design methodologies for ASIC's: architectual synthesis, logic synthesis, logic synthesis and module generation , 1989, DAC '89.
[4] Gary D. Hachtel,et al. BOLD: The Boulder Optimal Logic Design system , 1989, [1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track.
[5] Donald Ralph Schertz,et al. On the Representation of Digital Faults , 1969 .
[6] Kurt Keutzer,et al. Synthesis of robust delay-fault-testable circuits: theory , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[7] 藤原 秀雄,et al. Logic testing and design for testability , 1985 .
[8] Kurt Keutzer. DAGON: Technology Binding and Local Optimization by DAG Matching , 1987, DAC.
[9] Joseph L. A. Hughes. Multiple fault detection using single fault test sets , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[10] Sudhakar M. Reddy,et al. On the design of robust testable CMOS combinational logic circuits , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.
[11] Premachandran R. Menon,et al. Checkpoint Faults are not Sufficient Target Faults for Test Generation , 1986, IEEE Transactions on Computers.
[12] D. C. King. Diagnosis and reliable design of digital systems , 1977 .
[13] Robert K. Brayton,et al. MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[14] Michael H. Schulz,et al. Advanced automatic test pattern generation and redundancy identification techniques , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.
[15] Robert K. Brayton,et al. Multilevel logic synthesis , 1990, Proc. IEEE.
[16] S. Reddy,et al. On the design of robust multiple fault testable CMOS combinational logic circuits , 1988, ICCAD 1988.
[17] Robert K. Brayton,et al. Multi-level logic minimization using implicit don't cares , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[18] Kurt Keutzer,et al. Synthesis of robust delay-fault-testable circuits: practice , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[19] Gernot Metze,et al. On the Design of Multiple Fault Diagnosable Networks , 1971, IEEE Transactions on Computers.
[20] Michael H. Schulz,et al. SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[21] Wojciech Maly,et al. Realistic Fault Modeling for VLSI Testing , 1987, 24th ACM/IEEE Design Automation Conference.
[22] Gary D. Hachtel,et al. Verification algorithms for VLSI synthesis , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[23] Vinod K. Agarwal,et al. Multiple Fault Testing of Large Circuits by Single Fault Test Sets , 1981, IEEE Transactions on Computers.
[24] Gernot Metze,et al. A New Representation for Faults in Combinational Digital Circuits , 1972, IEEE Transactions on Computers.