A high voltage offset-gate SOS/MOS transistor

A high voltage SOS/MOS transistor with a new offset-gate structure is proposed and verified experimentally to realize completely dielectrically isolated high voltage CMOS ICs. Since its offset-gate region, consisting of a pinched resistor and an underlying substrate layer, is designed to deplete vertically throughout the silicon epi-layer at above the drain voltage equal to the offset-gate pinched-off voltage, the proposed transistor shows a high drain breakdown voltage characteristic that is not limited by the substrate doping level, but depends only on the offset-gate length. The offset-gate PMOS and NMOS transistors were successfully fabricated on the same intrinsic SOS wafer by ion implantation substrate doping and resulted in drain breakdown voltages of up to 950V and 1100V, respectively, at 100 µm offset-gate length.