A Novel Architecture for Implementation of Quasi Delay Insensitive Finite State Machines

Due to the increasing demand for mobile devices, the search for ultra-low-power projects is becoming a priority. One technique that allows a strong reduction of circuits dissipated power is the sub-threshold voltage operation, but it leads to some drawbacks. The QDI (Quasi Delay Insensitive) asynchronous circuits class shows to be an interesting solution to these problems, when compared to synchronous circuits and in CMOS-UDSM (Ultra Deep Sub-Micron) technology. Asynchronous finite state machines (AFSMs) are important components in an asynchronous system. This paper proposes a new architecture for QDI AFSMs described in Extended Burst-Mode specification, implemented in the dual-rail style using basic gates and memory based on RS latches. The resulting XBM_AFSMs are QDI, so they can operate in sub-threshold voltage. The architecture is presented through the case study and the obtained QDI_XBM_AFSM presents for three benchmarks an average reduction of 24.4%, and 48.3%, 49.6% and 49.2% respectively, latency time, number of LUTs, dynamic power and static power, when compared with four QDI controllers of the literature.

[1]  Shu-Chuan Huang,et al.  Synthesis of QDI FSMs from Synchronous Specifications , 2014, 2014 20th IEEE International Symposium on Asynchronous Circuits and Systems.

[2]  Yusuf Leblebici,et al.  Energy Efficiency Comparison of Asynchronous and Synchronous Circuits Operating in the Sub-Threshold Regime , 2008 .

[3]  Ross Smith,et al.  Asynchronous design using commercial HDL synthesis tools , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

[4]  Viacheslav Borisovich Marakhovsky,et al.  Globally asynchronous systems of interactive Moore state machines , 2016, IET Comput. Digit. Tech..

[5]  Duarte L. Oliveira,et al.  A design flow of asynchronous burst-mode circuits without fundamental-mode timing assumption , 2018, 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS).

[6]  Steve Furber,et al.  Principles of Asynchronous Circuit Design: A Systems Perspective , 2010 .

[7]  D. Dill,et al.  Automatic Synthesis of Extended Burst-Mode Circuits : Part II ( Automatic Synthesis ) , 1996 .

[8]  Omer Can Akgun,et al.  Minimum-Energy SubThreshold Self-Timed Circuits : Design Methodology and a Case Study , 2010 .

[9]  David Bol,et al.  Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic , 2009, ISLPED.

[10]  Bin Liu,et al.  A survey of dynamic power optimization techniques , 2003, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings..

[11]  Ran Ginosar,et al.  Implementing Sequential Machines as Self-Timed Circuits , 1992, IEEE Trans. Computers.

[12]  Ronald F. DeMara,et al.  Optimization of NULL convention self-timed circuits , 2004, Integr..

[13]  Alexandre Yakovlev,et al.  On Dual-Rail Control Logic for Enhanced Circuit Robustness , 2012, 2012 12th International Conference on Application of Concurrency to System Design.

[14]  Robust Synthesis of Asynchronous Burst-Mode Machines , 2005 .

[15]  G. Sicard,et al.  A modular synthesis method for low-power QDI state machines , 2011, 2011 IEEE 9th International New Circuits and systems conference.

[16]  G. Sicard,et al.  Optimizing speed and consumption of QDI controllers using direct mapping synthesis , 2009, 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference.

[17]  Alex Kondratyev,et al.  Design of Asynchronous Circuits Using Synchronous CAD Tools , 2002, IEEE Des. Test Comput..

[18]  Duarte L. Oliveira,et al.  Synthesis of QDI AFSMs from XBM specifications , 2018, 2018 2nd Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA).

[19]  Scott Hauck,et al.  Asynchronous design methodologies: an overview , 1995, Proc. IEEE.