System-level design solutions: Enabling the IoT explosion

Analysts estimate that there will be 50 billion internet-connected devices by 2020, from 25 billion in 2015. This predicted explosion of IoT devices affects various evolving and growing markets as well as entirely new applications. Despite the variety of target applications, all such devices demand low energy/power consumption, high reliability, connectivity, interoperability, security and privacy. Furthermore, while meeting all these demands, time-to-market is a critical metric determining whether an IoT product will capture market share and thus the greatest revenue opportunity. Thus, a design methodology that meets design goals while ensuring fast time-to-market is a critical need. In this paper, we discuss the vision and building blocks of such a design methodolgoy, which would hopefully become an enabling technology for future IoT development and growth.

[1]  Jason Cong,et al.  Efficient compilation of CUDA kernels for high-performance computing on FPGAs , 2013, TECS.

[2]  Ram Krishnamurthy,et al.  High-Performance Energy-Efficient Reconfigurable Accelerators/Co-processors for Tera-Scale Multi-core Microprocessors , 2010, ARC.

[3]  Manfred Josef Aigner,et al.  Security in the Internet of Things , 2010 .

[4]  Deming Chen,et al.  Behavioral-level IP integration in high-level synthesis , 2015, 2015 International Conference on Field Programmable Technology (FPT).

[5]  Deming Chen,et al.  JIT trace-based verification for high-level synthesis , 2015, 2015 International Conference on Field Programmable Technology (FPT).

[6]  Zhiru Zhang,et al.  High-level Synthesis for Low-power Design , 2015, IPSJ Trans. Syst. LSI Des. Methodol..

[7]  Deming Chen,et al.  A polyhedral-based SystemC modeling and generation framework for effective low-power design space exploration , 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[8]  Marimuthu Palaniswami,et al.  Internet of Things (IoT): A vision, architectural elements, and future directions , 2012, Future Gener. Comput. Syst..

[9]  John Seely Brown,et al.  The Origins of Ubiquitous Computing Research at PARC in the Late 1980s , 1999, IBM Syst. J..

[10]  Gary Smith,et al.  High-Level Synthesis: Past, Present, and Future , 2009, IEEE Design & Test of Computers.

[11]  Yun Liang,et al.  High level synthesis of stereo matching: Productivity, performance, and software constraints , 2011, 2011 International Conference on Field-Programmable Technology.

[12]  Jason Cong,et al.  FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs , 2009, 2009 IEEE 7th Symposium on Application Specific Processors.

[13]  Jason Cong,et al.  High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs , 2007, 2007 Asia and South Pacific Design Automation Conference.

[14]  Harry D. Foster.  Trends in functional verification: A 2014 industry study , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[15]  Matej Mohar,et al.  Security in Internet of Things , 2017 .

[16]  Yun Liang,et al.  High-level synthesis of multiple dependent CUDA kernels on FPGA , 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).