Extending the pseudo-stuck-at fault model to provide complete IDDQ coverage

Since its inception, the pseudo-stuck-at fault model has demonstrated its usefulness in generating IDDQ patterns, calculating coverage, and diagnosing defects. However, the model's definition has lacked rigor, which has resulted in multiple, incompatible, interpretations. This paper provides a complete definition for the model and demonstrates how variations will cause a loss of defect coverage. The covering relationship between the pseudo-stuck-at (PSA) model and leakage faults is proven for all combinational CMOS cells. This relationship is extended to show the effect that undetectable PSA faults have on leakage fault coverage. It is shown how to apply the model to sequential cells such as flip-flops and latches. The PSA model is also extended to cover both short and open faults in chip interconnect. A weighting function is introduced to tie the coverage more closely to process defect statistics. Finally, experimental results are given to show the effectiveness of the model on actual ASICs.

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