Low Power Montgomery Modular Multiplication on Reconfigurable Systems

This paper presents an area-optimized FPGA architecture of the Montgomery modular multiplication algorithm on a low power reconfigurable IGLOO © 2 FPGA of Microsemi ©. Our contributions consist of the mapping of the Montgomery algorithm to the specific architecture of the target FPGA, using the pipelined Math blocks and the embedded memory blocks. We minimize the occupation of these blocks as well as the usage of the regular FPGA cells (LUT4 and Flip Flops) through an dedicated scheduling algorithm. The obtained results suggest that a 224bit modular multiplication can be computed in 2.42 μs, at a cost of 444 LUT4, 160 Flip Flops, 1 Math Block and 1 64x18 RAM, with a power consumption of 25.35 mW. If more area resources are considered, modular multiplication can be performed in 1.30 μs at a cost of 658 LUT4, 268 Flip Flops, 2 Math Blocks, 2 64x18 RAMs and a power consumption of 36.02 mW.

[1]  C. D. Walter,et al.  Montgomery exponentiation needs no final subtractions , 1999 .

[2]  Çetin Kaya Koç,et al.  A Scalable Architecture for Montgomery Multiplication , 1999, CHES.

[3]  Lejla Batina,et al.  Montgomery in Practice: How to Do It More Efficiently in Hardware , 2002, CT-RSA.

[4]  Victor S. Miller,et al.  Use of Elliptic Curves in Cryptography , 1985, CRYPTO.

[5]  Joos Vandewalle,et al.  Hardware implementation of a Montgomery modular multiplier in a systolic array , 2003, Proceedings International Parallel and Distributed Processing Symposium.

[6]  Daniel J. Bernstein,et al.  Curve25519: New Diffie-Hellman Speed Records , 2006, Public Key Cryptography.

[7]  H. C. Williams,et al.  Advances in Cryptology — CRYPTO ’85 Proceedings , 2000, Lecture Notes in Computer Science.

[8]  Máire O'Neill,et al.  FPGA Montgomery multiplier architectures - a comparison , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[9]  P. L. Montgomery.  Modular multiplication without trial division , 1985 .

[10]  Gang Chen,et al.  A High-Performance Elliptic Curve Cryptographic Processor for General Curves Over ${\rm GF}(p)$ Based on a Systolic Arithmetic Unit , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[11]  Dipanwita Roy Chowdhury,et al.  Parallel crypto-devices for GF(p) elliptic curve multiplication resistant against side channel attacks , 2009, Comput. Electr. Eng..

[12]  Tim Güneysu,et al.  MicroACP - A Fast and Secure Reconfigurable Asymmetric Crypto-Processor - -Overhead Evaluation of Side-Channel Countermeasures- , 2014, ARC.

[13]  Paul Barrett,et al.  Implementing the Rivest Shamir and Adleman Public Key Encryption Algorithm on a Standard Digital Signal Processor , 1986, CRYPTO.

[14]  Hamad Alrimeih,et al.  Fast and Flexible Hardware Support for ECC Over Multiple Standard Prime Fields , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Tim Kerins,et al.  An FPGA implementation of a GF(p) ALU for encryption processors , 2004, Microprocess. Microsystems.

[16]  Adi Shamir,et al.  A method for obtaining digital signatures and public-key cryptosystems , 1978, CACM.

[17]  Ingrid Verbauwhede,et al.  A compact FPGA-based architecture for elliptic curve cryptography over prime fields , 2010, ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors.

[18]  Whitfield Diffie,et al.  New Directions in Cryptography , 1976, IEEE Trans. Inf. Theory.

[19]  Ingrid Verbauwhede,et al.  Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems , 2006, ARC.

[20]  S KaliskiBurton,et al.  Analyzing and Comparing Montgomery Multiplication Algorithms , 1996 .

[21]  Tolga Acar,et al.  Analyzing and comparing Montgomery multiplication algorithms , 1996, IEEE Micro.

[22]  Shuichi Ichikawa,et al.  Implementation and Evaluation of Modular Multiplication Based on Coarsely Integrated Operand Scanning , 2012, 2012 Third International Conference on Networking and Computing.

[23]  Jakob Jonsson,et al.  Public-Key Cryptography Standards (PKCS) #1: RSA Cryptography Specifications Version 2.1 , 2003, RFC.

[24]  Johannes Merkle,et al.  Elliptic Curve Cryptography (ecc) Brainpool Standard Curves and Curve Generation , 2010 .

[25]  Vipul Gupta,et al.  A public-key cryptographic processor for RSA and ECC , 2004, Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004..

[26]  Paul C. Kocher,et al.  Differential Power Analysis , 1999, CRYPTO.

[27]  Tim Güneysu,et al.  MicroECC: A Lightweight Reconfigurable Elliptic Curve Crypto-processor , 2011, 2011 International Conference on Reconfigurable Computing and FPGAs.

[28]  J. Solinas.  CORR 99-39 Generalized Mersenne Numbers , 1999 .

[29]  Xiaojun Wang,et al.  Efficient montgomery multiplier for pairing and elliptic curve based cryptography , 2014, 2014 9th International Symposium on Communication Systems, Networks & Digital Sign (CSNDSP).

[30]  Shreyas Sundaram,et al.  A public-key cryptographic processor for RSA and ECC , 2004 .

[31]  Christof Paar,et al.  A Scalable GF(p) Elliptic Curve Processor Architecture for Programmable Hardware , 2001, CHES.

[32]  Paulo S. L. M. Barreto,et al.  A note on high-security general-purpose elliptic curves , 2013, IACR Cryptol. ePrint Arch..

[33]  Christof Paar,et al.  High-Radix Montgomery Modular Exponentiation on Reconfigurable Hardware , 2001, IEEE Trans. Computers.