A DATA FLOW ARCHITECTURE WITH IMPROVED ASYMPTOTIC

Large scale integration presents a unique opportunity to design a computer compromising large numbers of small, inexpensive processors. This paper presents a design for such a machine based on the asynchronous and functional semantics of data flow. Processors within the machine are interconnected by a packet-switched binary n-cube although a limited number of other networks may be substituted with predictable asymptotic effects on performance. Improved performance of the proposed machine over a previously reported data flow architecture is predicted in terms of the computational time complexity of several example programs: matrix multiply, quicksort, and iterative solutions to partial differential equations. Although the example programs are numerical in nature, the machine is intended for general-purpose computations since programs are written in the high level data flow language Id without knowledge of the number of processors or interconnections. New storage management and data communication methods are also presented which are necessary to obtain the improved performance. Experimental results from a simulated machine incorporating some of these methods are given to corroborate analytic results.