High-Voltage Lateral Double-Diffused Metal-Oxide Semiconductor with Double Superjunction

[1]  Hang Yang,et al.  Optimization of novel superjunction LDMOS with partial low K layer , 2018, Superlattices and Microstructures.

[2]  Yintang Yang,et al.  Theory Analyses of SJ-LDMOS With Multiple Floating Buried Layers Based on Bulk Electric Field Modulation , 2018, IEEE Transactions on Electron Devices.

[3]  Hang Yang,et al.  A novel superjunction lateral double-diffused MOS with segmented buried P-layer , 2018 .

[4]  Junji Cheng,et al.  An Improved SOI P-Channel LDMOS With High- ${k}$ Gate Dielectric and Dual Hole-Conductive Paths , 2017, IEEE Electron Device Letters.

[5]  Yan Gu,et al.  Novel Superjunction LDMOS (>950 V) With a Thin Layer SOI , 2017, IEEE Electron Device Letters.

[6]  Gaofeng Wang,et al.  Multiple Trench Split-gate SOI LDMOS Integrated With Schottky Rectifier , 2017, IEEE Transactions on Electron Devices.

[7]  Ying Wang,et al.  Analytical Model and Optimization for Variable Drift Region Width SOI LDMOS Device , 2016, IEEE Transactions on Electron Devices.

[8]  Bo Zhang,et al.  Equivalent Substrate Model for Lateral Super Junction Device , 2014, IEEE Transactions on Electron Devices.

[9]  Q. Wang,et al.  Ultralow Specific On-Resistance Superjunction Vertical DMOS With High-$K$ Dielectric Pillar , 2012, IEEE Electron Device Letters.

[10]  Xinhong Cheng,et al.  Realization of 850V breakdown voltage LDMOS on Simbond SOI , 2012 .

[11]  S.G. Nassif-Khalil,et al.  SJ/RESURF LDMOST , 2004, IEEE Transactions on Electron Devices.

[12]  Chenming Hu,et al.  Optimum doping profile for minimum ohmic resistance and high-breakdown voltage , 1979 .

[13]  Chenming Hu.  Optimum doping profile for minimum ohmic resistance and high-breakdown voltage , 1979, IEEE Transactions on Electron Devices.