Hierarchical Analysis of a Distributed Evaluator

We outline the analysis of a distributed evaluator for an applicative language FGL (Function Graph Language). Our goal is to show that the least fixed point semantics of FGL are faithfully implemented by the hardware evaluator envisioned in tne Applicative Multi-Processor System AMPS. Included in the analysis are a formalization of demand-driven computation , the' i n t r oduc t i on of an intermediate graphic language IGL to aid in our proofs, and discussion of pragmatic issues involved in the AMPS machine language design.