A cost effective 2-D adaptive block size IDCT architecture for HEVC standard

High Efficiency Video Coding (HEVC) is the currently developing video coding standard by the MPEG and ITU organizations. Unlike previous video codec standards, HEVC employs variable block size integer DCT/IDCT to conduct spatial redundancy compression. In this paper, a novel 2-D IDCT VLSI architecture for HEVC standard is presented. Using adaptive block size scheduling scheme, the proposed architecture supports variable block size IDCT from 4×4 to 32×32 pixels with low hardware overhead while keeping the highest performance. Using TSMC 65nm 1P9M technology, the synthesis result shows that the 2-D architecture achieves the maximum work frequency at 400MHz and the hardware cost is about 112.5K Gates. Experimental results show that the proposed architecture is able to deal with real-time adaptive HEVC IDCT of 4K×2K (4096×2048)@30fps video sequence at 179.4MHz. In consequence, it offers a cost-effective solution for the future UHD applications.

[1]  Jeong-Hoon Park,et al.  Block Partitioning Structure in the HEVC Standard , 2012, IEEE Transactions on Circuits and Systems for Video Technology.

[2]  Gary J. Sullivan,et al.  Overview of the High Efficiency Video Coding (HEVC) Standard , 2012, IEEE Transactions on Circuits and Systems for Video Technology.

[3]  Seongsoo Lee,et al.  2-D Large Inverse Transform (16×16, 32×32) for HEVC (High Efficiency Video Coding) , 2012 .

[4]  A. Madanayake,et al.  A multiplication-free digital architecture for 16×16 2-D DCT/DST transform for HEVC , 2012, 2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel.

[5]  Khan A. Wahid,et al.  A cost effective implementation of 8×8 transform of HEVC from H.264/AVC , 2012, 2012 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE).

[6]  Colin Doutre,et al.  HEVC: The New Gold Standard for Video Compression: How Does HEVC Compare with H.264/AVC? , 2012, IEEE Consumer Electronics Magazine.

[7]  Gary J. Sullivan,et al.  Rate-constrained coder control and comparison of video coding standards , 2003, IEEE Trans. Circuits Syst. Video Technol..

[8]  M. Grellert,et al.  Low cost and high throughput multiplierless design of a 16 point 1-D DCT of the new HEVC video coding standard , 2012, 2012 VIII Southern Conference on Programmable Logic.

[9]  Weiwei Shen,et al.  A Unified 4/8/16/32-Point Integer IDCT Architecture for Multiple Video Coding Standards , 2012, 2012 IEEE International Conference on Multimedia and Expo.

[10]  Ajay Luthra,et al.  Overview of the H.264/AVC video coding standard , 2003, IEEE Trans. Circuits Syst. Video Technol..