Effect of traps-to-gate tunnel communication on C-V characteristics of MIS capacitors
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[1] Nadine Collaert,et al. An Analytical Model of MOS Admittance for Border Trap Density Extraction in High- $k$ Dielectrics of III–V MOS Devices , 2016, IEEE Transactions on Electron Devices.
[2] B. Majkusiak,et al. Small-signal admittance model of multi-traps distributed over energy and space in the insulator of MIS tunnel structures , 2015 .
[3] L. Larcher,et al. A New Physical Method Based on $CV$ – $GV$ Simulations for the Characterization of the Interfacial and Bulk Defect Density in High- $k$ /III-V MOSFETs , 2015, IEEE Transactions on Electron Devices.
[4] Yuan Taur,et al. Interface-State Modeling of $\hbox{Al}_{2}\hbox{O}_{3}$ –InGaAs MOS From Depletion to Inversion , 2012, IEEE Transactions on Electron Devices.
[5] M. Rodwell,et al. A Distributed Bulk-Oxide Trap Model for $\hbox{Al}_{2} \hbox{O}_{3}$ InGaAs MOS Devices , 2012, IEEE Transactions on Electron Devices.
[6] M. Rodwell,et al. A Distributed Model for Border Traps in MOS Devices , 2011 .
[7] E. H. Nicollian,et al. Mos (Metal Oxide Semiconductor) Physics and Technology , 1982 .
[8] W. Dahlke,et al. Theory of tunneling into interface states , 1970 .