Testability of Switching Lattices in the Stuck at Fault Model

Switching lattices are two-dimensional arrays of four-terminal switches proposed in a seminal paper by Akers in 1972 to implement Boolean functions. Recently, with the advent of a variety of emerging nanoscale technologies based on regular arrays of switches, synthesis methods targeting lattices of multi-terminal switches have found a renewed interest. In this paper, the testability under the stuck-at-fault model (SAFM) of switching lattices is analyzed, and properties of fully testable lattices are identified and discussed. Experimental results are given to analyze the testability of lattices synthesized with different methods.

[1]  Marc D. Riedel,et al.  Logic Synthesis for Switching Lattices , 2012, IEEE Transactions on Computers.

[2]  S. Yang,et al.  Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 , 1991 .

[3]  Mustafa Altun,et al.  Synthesis and Optimization of Switching Nanoarrays , 2015, 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

[4]  Rolf Drechsler,et al.  Testability of SPP Three-Level Logic Networks in Static Fault Models , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Tiziano Villa,et al.  Logic Minimization and Testability of 2-SPP Networks , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Mustafa Altun,et al.  Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Tiziano Villa,et al.  Enhancing logic synthesis of switching lattices by generalized Shannon decomposition methods , 2018, Microprocess. Microsystems.

[8]  Peter J. Stuckey,et al.  Synthesizing Optimal Switching Lattices , 2014, TODE.

[9]  Thomas W. Williams,et al.  Design for Testability - A Survey , 1982, IEEE Trans. Computers.

[10]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[11]  Valentina Ciriani,et al.  Synthesis on switching lattices of Dimension-reducible Boolean functions , 2016, 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

[12]  Mustafa Altun,et al.  Logic synthesis and defect tolerance for memristive crossbar arrays , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[13]  Mustafa Altun,et al.  A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays , 2018, ACM Comput. Surv..

[14]  Mehdi Baradaran Tahoori,et al.  Computing with nano-crossbar arrays: Logic synthesis and fault tolerance , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[15]  Dan Alexandrescu,et al.  Logic synthesis and testing techniques for switching nano-crossbar arrays , 2017, Microprocess. Microsystems.

[16]  Sheldon B. Akers.  A Rectangular Logic Array , 1972, IEEE Transactions on Computers.

[17]  Tiziano Villa,et al.  Logic Minimization and Testability of 2SPP-P-Circuits , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

[18]  Valentina Ciriani,et al.  Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis , 2017, 2017 Euromicro Conference on Digital System Design (DSD).