Spectroscopy of SILC trap locations and spatial correlation study of percolation path in the high-κ and interfacial layer

It has always been assumed all along that the percolation path in the high-κ (HK) and interfacial layer (IL) of dual layer dielectric stacks are perfectly aligned with each other. There is however no solid evidence to date to support this assumption because the standard stress levels applied and compliance chosen for time dependent dielectric breakdown (TDDB) tests is high enough to instantaneously rupture both the HK and IL layers, once one of them reaches the percolation stage of degradation. The aim of this study is to probe the location of the HK and IL percolation paths and study their correlation by means of a novel TDDB test algorithm that enables a finite time two-stage event of BD for the dual layer stack with only one dielectric percolating during each stage of stress. The analysis reveals that although in most cases the HK and IL layers have the BD location very close to each other, there are cases of slight misalignment that can be advantageous from a reliability viewpoint as misaligned percolation paths result in a much lower leakage current (even in the logarithmic scale) as compared to the perfectly aligned ones. We also extend this analysis to probing the locations of different stress induced leakage current (SILC) defect clusters in the dielectric prior to any breakdown event.

[1]  J. Sune,et al.  Analytical Cell-Based Model for the Breakdown Statistics of Multilayer Insulator Stacks , 2009, IEEE Electron Device Letters.

[2]  X. Wu,et al.  Role of grain boundary percolative defects and localized trap generation on the reliability statistics of high-κ gate dielectric stacks , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[3]  B. Kaczer,et al.  Theory of Breakdown Position Determination by Voltage- and Current-Ratio Methods , 2008, IEEE Transactions on Electron Devices.

[4]  E. Miranda,et al.  Analytic model for the post-breakdown current in HfO2/TaN/TiN gate stacks , 2007, 2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits.

[5]  Bonnie E. Weir,et al.  Gate dielectric breakdown in the time-scale of ESD events , 2005, Microelectron. Reliab..

[6]  J. W. McPherson,et al.  Time dependent dielectric breakdown physics - Models revisited , 2012, Microelectron. Reliab..

[7]  L. Larcher,et al.  Breakdown in the metal/high-k gate stack: Identifying the “weak link” in the multilayer dielectric , 2008, 2008 IEEE International Electron Devices Meeting.

[8]  N. Raghavan,et al.  New statistical model to decode the reliability and weibull slope of high-κ and interfacial layer in a dual layer dielectric stack , 2010, 2010 IEEE International Reliability Physics Symposium.

[9]  Xing Wu,et al.  Oxygen-Soluble Gate Electrodes for Prolonged High-$ \kappa$ Gate-Stack Reliability , 2011, IEEE Electron Device Letters.

[10]  G. Bersuker,et al.  PROGRESSIVE BREAKDOWN CHARACTERISTICSOFHIGH-K/METAL GATE , 2007 .

[11]  Rampi Ramprasad,et al.  Diffusion of O vacancies nearSi:HfO2interfaces: Anab initioinvestigation , 2007 .

[12]  J. Stathis.  Percolation models for gate oxide breakdown , 1999 .

[13]  James H. Stathis,et al.  Multiple breakdown phenomena and modeling for non-uniform dielectric systems , 2014, 2014 IEEE International Electron Devices Meeting.

[14]  Nagarajan Raghavan,et al.  Identifying the First Layer to Fail in Dual-Layer ${\rm SiO}_{\rm x}/{\rm HfSiON}$ Gate Dielectric Stacks , 2013, IEEE Electron Device Letters.

[15]  Alexander L. Shluger,et al.  The interaction of oxygen vacancies with grain boundaries in monoclinic HfO2 , 2009 .

[16]  Yoon-Ha Jeong,et al.  Interfacial-Layer-Driven Dielectric Degradation and Breakdown of HfSiON/SiON Gate Dielectric nMOSFETs , 2011, IEEE Electron Device Letters.

[17]  S. De Gendt,et al.  Failure Defects Observed in Post-Breakdown High-κ/Metal Gate Stack Mosfet , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[18]  N. Horiguchi,et al.  Study of (correlated) trap sites in SILC, BTI and RTN in SiON and HKMG devices , 2014, Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).

[19]  T. Nigam,et al.  TDDB failure distribution of metal gate/high-k CMOS devices on SOI substrates , 2009, 2009 IEEE International Reliability Physics Symposium.

[20]  Marc Porti,et al.  Reliability of SiO2 and high-k gate insulators: A nanoscale study with conductive atomic force microscopy , 2007 .

[21]  Byoung Hun Lee,et al.  Effect of the Interfacial Layer in High- Gate Stacks on NBTI , 2008 .

[22]  Guido Groeseneken,et al.  Relation between breakdown mode and location in short-channel nMOSFETs and its impact on reliability specifications , 2001 .

[23]  T. Nigam,et al.  Accurate model for time-dependent dielectric breakdown of high-k metal gate stacks , 2009, 2009 IEEE International Reliability Physics Symposium.

[24]  Barry P. Linder,et al.  The effect of interface thickness of high-k/metal gate stacks on NFET dielectric reliability , 2009, 2009 IEEE International Reliability Physics Symposium.

[25]  W.L. Chang,et al.  Role of interface layer in stress-induced leakage current in high-k/metal-gate dielectric stacks , 2010, 2010 IEEE International Reliability Physics Symposium.

[26]  R. K. Smith,et al.  A phenomenological theory of correlated multiple soft-breakdown events in ultra-thin gate dielectrics , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[27]  L. Larcher,et al.  The “buffering” role of high-к in post breakdown degradation immunity of advanced dual layer dielectric gate stacks , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[28]  Kin Leong Pey,et al.  Breakdowns in high-k gate stacks of nano-scale CMOS devices , 2005 .

[29]  D.S.H. Chan,et al.  Analysis of charge trapping and breakdown mechanism in high-k dielectrics with metal gate electrode using carrier separation , 2003, IEEE International Electron Devices Meeting 2003.

[30]  Byoung Hun Lee,et al.  Stress field analysis to understand the breakdown characteristics of stacked high-k dielectrics , 2009 .

[31]  M. Rafik,et al.  High-K gate stack breakdown statistics modeled by correlated interfacial layer and high-k breakdown path , 2010, 2010 IEEE International Reliability Physics Symposium.

[32]  Yoon-Ha Jeong,et al.  RF and hot carrier effects in metal gate/high-k dielectric nMOSFETs at cryogenic temperature , 2009, 2009 IEEE International Reliability Physics Symposium.