In this work, we present a hardware implementation of the encryption algorithm YAEA. The basic notion behind this encryption technique is a sequential search in a random binary file for an octet that represents the ASCII number of the plain-text character. Recording the location of this octet, one is able to assemble a file of near or far pointers to the locations of various octets. Rather inaccurately, we call this file the ciphered text. However, this file contains only pointers to the locations of the searched octets. Since there is negligible correlation between the pointer file and the plain-text characters, the method, we believe, is robust against any type of cipher attacks. The hardware implementation utilizes Field Programmable Gate Array Technology (FPGA) and the hardware description language VHDL to conclude the realization. The basic microarchitecture of the encryption processor consists of a random binary number generator, an encryption-processing unit and a specially designed sequential memory unit. Furthermore, we demonstrate the results of various performance tests that we have carried out on the architecture. These tests were performed taking into considerations certain real-time applications.
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