Enhanced low-power high-speed adder for error-tolerant application
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Gang Wang | Kiat Seng Yeo | Ning Zhu | Wang Ling Goh | G. Wang | K. Yeo | W. Goh | Ning Zhu
[1] Melvin A. Breuer,et al. An Illustrated Methodology for Analysis of Error Tolerance , 2008, IEEE Design & Test of Computers.
[2] Antonio Ortega,et al. Hardware testing for error tolerant multimedia compression based on linear transforms , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).
[3] Melvin A. Breuer,et al. Error-tolerance and multi-media , 2006, 2006 International Conference on Intelligent Information Hiding and Multimedia.
[5] M. Lehman,et al. Skip Techniques for High-Speed Carry-Propagation in Binary Arithmetic Units , 1961, IRE Trans. Electron. Comput..
[6] Orest J. Bedrij. Carry-Select Adder , 1962, IRE Trans. Electron. Comput..
[7] Melvin A. Breuer,et al. A novel test methodology based on error-rate to support error-tolerance , 2005, IEEE International Conference on Test, 2005..
[8] Melvin A. Breuer,et al. Let's think analog , 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).
[9] Zhi-Hui Kong,et al. Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[10] Antonio Ortega,et al. Analysis and testing for error tolerant motion estimation , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).
[11] O. L. Macsorley. High-Speed Arithmetic in Binary Computers , 1961, Proceedings of the IRE.