A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs

This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing noise of the CIS by one over the square root of the number of samplings. The area of the 12-bit SAR ADC is reduced by using a 10-bit capacitor digital-to-analog converter (DAC) with four scaled reference voltages. In addition, a simple up/down counter-based digital processing logic is proposed to perform complex calculations for multiple sampling and digital correlated double sampling. To verify the proposed multiple sampling method, a 256 × 128 pixel array CIS with 12-bit SAR ADCs was fabricated using 0.18 μm CMOS process. The measurement results shows that the proposed multiple sampling method reduces each A/D conversion time from 1.2 μs to 0.45 μs and random noise from 848.3 μV to 270.4 μV, achieving a dynamic range of 68.1 dB and an SNR of 39.2 dB.

[1]  Shoji Kawahito,et al.  Column-Parallel Correlated Multiple Sampling Circuits for CMOS Image Sensors and Their Noise Reduction Effects , 2010, Sensors.

[2]  Jae-Hong Kim,et al.  A 14b extended counting ADC implemented in a 24Mpixel APS-C CMOS image sensor , 2012, 2012 IEEE International Solid-State Circuits Conference.

[3]  A. Theuwissen,et al.  Column-Parallel Digital Correlated Multiple Sampling for Low-Noise CMOS Image Sensors , 2012, IEEE Sensors Journal.

[4]  S. Kawahito,et al.  Noise analysis of high-gain, low-noise column readout circuits for CMOS image sensors , 2004, IEEE Transactions on Electron Devices.

[5]  Yao Suying,et al.  Analysis of incomplete charge transfer effects in a CMOS image sensor , 2013 .

[6]  H. S. Wolff,et al.  iRun: Horizontal and Vertical Shape of a Region-Based Graph Compression , 2022, Sensors.

[7]  Minho Kwon,et al.  A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[8]  Yaowu Mo,et al.  8.9-Megapixel Video Image Sensor With 14-b Column-Parallel SA-ADC , 2009, IEEE Transactions on Electron Devices.

[9]  K. Isobe,et al.  A High-Speed Low-Noise CMOS Image Sensor With 13-b Column-Parallel Single-Ended Cyclic ADCs , 2009, IEEE Transactions on Electron Devices.

[10]  Suat U. Ay.  A 1.32pW/frame•pixel 1.2V CMOS energy-harvesting and imaging (EHI) APS imager , 2011, 2011 IEEE International Solid-State Circuits Conference.

[11]  Kyungmin Kim,et al.  A 1.1e- temporal noise 1/3.2-inch 8Mpixel CMOS image sensor using pseudo-multiple sampling , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[12]  Marvin H. White,et al.  Characterization of surface channel CCD image arrays at low light levels , 1974 .

[13]  Amine Bermak,et al.  A 64 fJ/step 9-bit SAR ADC Array With Forward Error Correction and Mixed-Signal CDS for CMOS Image Sensors , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[14]  Albert M. Fowler,et al.  Noise reduction strategy for hybrid IR focal-plane arrays , 1991, Optics & Photonics.

[15]  Brian P. Ginsburg,et al.  An energy-efficient charge recycling approach for a SAR converter with capacitive DAC , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[16]  Amine Bermak,et al.  A Low-Power Pilot-DAC Based Column Parallel 8b SAR ADC With Forward Error Correction for CMOS Image Sensors , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[17]  Oh-Kyong Kwon,et al.  A Low-Power CMOS Image Sensor With Area-Efficient 14-bit Two-Step SA ADCs Using Pseudomultiple Sampling Method , 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

[18]  Tomoyuki Noda,et al.  A 1/2.7 inch Low-Noise CMOS Image Sensor for Full HD Camcorders , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[19]  Shoji Kawahito,et al.  A Low-Noise High Intrascene Dynamic Range CMOS Image Sensor With a 13 to 19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC , 2012, IEEE Journal of Solid-State Circuits.

[20]  Suat U. Ay,et al.  An Ultra-Low Power Energy Harvesting and Imaging (EHI) Type CMOS APS Imager With Self-Power Capability , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[21]  Minho Kwon,et al.  A 2.1 M Pixels, 120 Frame/s CMOS Image Sensor With Column-Parallel $\Delta \Sigma$ ADC Architecture , 2011, IEEE Journal of Solid-State Circuits.