Design of low-jitter 1-GHz phase-locked loops for digital clock generation
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A 1-GHz phase-locked loop (PLL) is implemented in 0.5-/spl mu/m CMOS to generate a 500-MHz clock with 50% duty. The voltage-controlled oscillator (VCO) combined with the differential charge pump is employed to have low clock skew and better immunity to the noises from supply, ground and substrate. The long-term peak-to-peak jitter of less than 70 psec and 165 psec are achieved for the quiet supply line and for the noisy one modulated by 400-mV/sub p-p/, 500-kHz square wave, respectively. The prototype 1-GHz PLL consumes 55 mW with 3.3-V supply. The PLL with the phase interpolation technique is also investigated and its performance is compared to the standard approach.
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