Correlation of picosecond laser-induced latchup and energetic particle-induced latchup in CMOS test structures

We show that the thresholds for picosecond (psec) laser pulse-induced latchup and energetic particle-induced latchup are well correlated over a range of bulk CMOS test structures designed to be susceptible to latchup. The spatial length of the latchup-sensitive node of the test structures covers a range of values that commonly occur in bulk CMOS devices. The accuracy of this correlation implies that laser-induced latchup can be used for hardness assurance and, under the proper conditions, can be an accurate predictor of latchup threshold linear energy transfer (LET) for most bulk CMOS devices.

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