Design of Verilog-HDL Based Simulator for Network on Chips

Network on Chips (NoCs) are proposed to solve communication bandwidth limitation in modern Multi-Processors System on Chip (MPSoC) systems. Researchers (prove) relies their proposed ideas using modeling and simulation to evaluate the performance of their novel ideas. In this paper, we present a Verilog-HDL based simulator for NoCs. It considered as a cycle-accurate simulator to simulate the real environment of NoCs. It has a set of parameters that can be modify for a determined test. Also, it has the capability to add and remove any of network or router components.