Nanoscale FinFETs with gate-source/drain underlap

Using two-dimensional numerical device simulations, we show that optimally designed nanoscale FinFETs with undoped bodies require gate-source/drain (G-S/D) underlap that can be effectively achieved via large, doable straggle in the S-D fin-extension doping profile without causing S-D punch-through. The effective underlap significantly relaxes the fin-thickness requirement for control of short-channel effects (SCEs) via a bias-dependent effective channel length (L/sub eff/), which is long in weak inversion and approaches the gate length in strong inversion. Dependence of L/sub eff/ on the S/D doping profile defines a design tradeoff regarding SCEs and S/D series resistance that can be optimized, depending on the fin width, via engineering of the doping profile in the S/D fin-extensions. The noted optimization is exemplified via a well-tempered FinFET design with an 18-nm gate length, showing further that designs with effective underlap yield minimal parasitic capacitance and reduce leakage components such as gate-induced drain leakage current.

[1]  J. G. Fossum,et al.  Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs , 2002 .

[2]  G. O. Workman,et al.  A process/physics-based compact model for nonclassical CMOS device and circuit design , 2004 .

[3]  Robert W. Dutton,et al.  Impact of lateral source/drain abruptness on device performance , 2002 .

[4]  Hyung-Kyu Lim,et al.  Threshold voltage of thin-film Silicon-on-insulator (SOI) MOSFET's , 1983, IEEE Transactions on Electron Devices.

[5]  Jerry G. Fossum,et al.  Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low-voltage CMOS technology , 1995 .

[6]  T. Skotnicki,et al.  2D QM simulation and optimization of decanano non-overlapped MOS devices , 2003, IEEE International Electron Devices Meeting 2003.

[7]  Bin Yu,et al.  FinFET scaling to 10 nm gate length , 2002, Digest. International Electron Devices Meeting,.

[8]  Chenming Hu,et al.  Sub 50-nm FinFET: PMOS , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[9]  J. An,et al.  Physical insights on design and modeling of nanoscale FinFETs , 2003, IEEE International Electron Devices Meeting 2003.

[10]  Keunwoo Kim,et al.  Double-gate CMOS: symmetrical- versus asymmetrical-gate devices , 2001 .

[11]  T. Skotnicki,et al.  16 nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimisation , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[12]  M. Fischetti,et al.  Monte Carlo simulation of double-gate silicon-on-insulator inversion layers: The role of volume inversion , 2001 .

[13]  V. Trivedi,et al.  Scaling fully depleted SOI CMOS , 2003 .

[14]  Yuan Taur,et al.  On "effective channel length" in 0.1-μm MOSFETs , 1995, IEEE Electron Device Letters.

[15]  Ying Zhang,et al.  Extension and source/drain design for high-performance FinFET devices , 2003 .

[16]  Borivoje Nikolic,et al.  Circuit-Performance Implications for Double-Gate MOSFET Scaling below 25 nm , 2003 .

[17]  Krishna C. Saraswat,et al.  Optimization of extrinsic source/drain resistance in ultrathin body double-gate FETs , 2003 .

[18]  Michael Specht,et al.  Impact of technology parameters on device performance of UTB-SOI CMOS , 2004 .