A 60 GHz CMOS-SOI Stacked Push-Push Frequency Doubler with 12 dBm Output Power and 20% Efficiency

This paper presents a stacked push-push frequency doubler using an inductive source degeneration technique for generating high power millimeter-wave frequency signals. A balanced second harmonic trapping matching network is also added at the input to enhance the power efficiency. The 60 GHz frequency doubler demonstrator, designed using 45-nm CMOS SOI technology, showed a peak output power of 12dBm, DC-to-RF efficiency of 20%, and a peak conversion gain of 2.1 dB. By applying a low-complexity digital pre-distortion scheme, the designed doubler was successfully used to generate a 200 MHz vector modulated signal with an error vector magnitude of 2.9% and an average efficiency of 12%.