Studying the impacts of loop unrolling and pipeline in the FPGA design of the Simon and RoadRunneR lightweght ciphers

In this work, the impacts of the loop unrolling and pipeline in the FPGA implementation of the Simon and RoadRunneR lightweight ciphers is studied. To achieve this, two basic architectures were used. In the first architecture only loop unrolling is applied while, the second one supports both the loop unrolling and pipeline. Using these architectures, three designs versions were developed, for each algorithm. The first and second ones concern individually the encryption and decryption procedures while, the third version is a hybrid one that supports both encryption and decryption. The metrics that were studied the area, frequency, throughput, throughput/area and energy consumption. The produced designs were implemented in Xilinx (Kintex-7) FPGA technology. Based on the implementation results, a detailed study on the above-mentioned design metrics was performed and important outcomes were derived.