EPICURE: A partitioning and co-design framework for reconfigurable computing

This paper presents a new global design methodology capable to bridge the gap between an abstract specification level and a heterogeneous reconfigurable architecture level. The Epicure contribution is the result of a joint study on abstraction/refinement methods and a smart reconfigurable architecture within the formal Esterel design tools suite. The original points of this work are : i) a generic HW/SW interface model, ii) a specification methodology that handles the control, includes efficient verification and HW/SW synthesis capabilities, iii) a method for parallelism exploration based on abstract resources/performance estimation expressed in terms of area/delay tradeoffs, iv) a HW/SW partitioning approach that refines the specification into explicit HW configurations and the associated SW control. The Epicure framework shows how a cooperation of complementary methodologies and CAD tools associated with a relevant architecture can significantly improve the designer productivity, especially in the context of reconfigurable architectures.

[1]  Jean Luc Philippe,et al.  Fast prototyping of reconfigurable architectures from a C program , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[2]  Jean-Philippe Diguet,et al.  A Power Aware System-Level Design Space Exploration Framework , 2002 .

[3]  Charles André Representation and Analysis of Reactive Behaviors: A Synchronous Approach , 2000 .

[4]  G. Plotkin,et al.  Proof, language, and interaction: essays in honour of Robin Milner , 2000 .

[5]  ScienceDirect Microprocessors and microsystems , 1978 .

[6]  Mohamed Abid,et al.  Multi-granularity metrics for the era of strongly personalized SOCs , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[7]  Niraj K. Jha,et al.  COSYN: hardware-software co-synthesis of embedded systems , 1997, DAC.

[8]  Ed F. Deprettere,et al.  System level design with SPADE: an M-JPEG case study , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[9]  Jorg Henkel,et al.  System-level exploration for pareto-optimal configurations in parameterized systems-on-a-chip , 2001, ICCAD 2001.

[10]  Michel Auguin,et al.  Partitioning Reactive Data Flow Applications On Dynamically Reconfigurable Systems , 2003, VLSI-SOC.

[11]  Jos T. J. van Eijndhoven,et al.  A Taxonomy of Custom Computing Machines , 2000 .

[12]  Jörg Henkel,et al.  System-level exploration for Pareto-optimal configurations in parameterized systems-on-a-chip , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[13]  Jean Luc Philippe,et al.  Design-Trotter: System-level dynamic estimation task a first step towards platform architecture selection , 2005, J. Embed. Comput..

[14]  Gérard Berry,et al.  The foundations of Esterel , 2000, Proof, Language, and Interaction.

[15]  Erik Stoy,et al.  Aspects on system-level design , 1999, Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450).

[16]  Frédéric Boussinot,et al.  The ESTEREL language , 1991, Proc. IEEE.

[17]  Jean Luc Philippe,et al.  Design-Trotter: a multimedia embedded systems design space exploration tool , 2002, 2002 IEEE Workshop on Multimedia Signal Processing..