Device and circuit models of InAlN/GaN D- and dual-gate E-mode HEMTs for design and characterisation of monolithic NAND logic cell

In this paper, we present the monolithic integration of enhancement-mode and depletion-mode InAlN/GaN heterostructure high electron mobility transistors (HEMTs). The aim of the work is to show the results of the designed NAND logic cell which consists of the enhancement-mode dual-gate HEMT transistor and the depletion-mode HEMT transistor integrated onto a single die. We present well calibrated electrophysical models for 2-D device simulations employing Sentaurus Device from Synopsys. Sentaurus Device mixed-mode setup interconnects both transistor types to NAND logic cell circuit which allows analysis and characterization of the device as the complex system. New circuit nonlinear models of depletion-mode and dual-gate enhancement-mode HEMTs are proposed and calibrated by experimental results. The proposed models exhibit more accurate results. Good agreement between measurements and simulations confirms the validity of the proposed models and simulation methodology.

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