Single-Ended 10T SRAM Cell with High Yield and Low Standby Power

This paper introduces a 10T single-ended SRAM cell with high stability and low static power. The read static noise margin is augmented by using a Schmitt-trigger inverter and decoupling the storage node from the read bitline by adding one transistor. Since writing “1” is difficult in single-ended SRAM cells, using proper capacitive coupling and also extra pMOS transistor as an access transistor mitigates the problem. To evaluate read, write, and hold yields, we performed 10,000 Monto Carlo simulations in the 32-nm technology, and the results show our cell has 7.5×, 1.4×, and 1.1 × more yields than that of the conventional 6T SRAM cell. The proposed cell also has the least static power consumption. This amount is 1.5× less than the conventional 6T at the supply voltage of 0.5 V.

[1]  Hai Huang,et al.  Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Hanwool Jeong,et al.  Design of a 22-nm FinFET-Based SRAM With Read Buffer for Near-Threshold Voltage Operation , 2015, IEEE Transactions on Electron Devices.

[3]  Mohd. Hasan,et al.  Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  K. Roy,et al.  A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM , 2007, IEEE Journal of Solid-State Circuits.

[5]  Debiprasad Priyabrata Acharya,et al.  A high stable 8T-SRAM with bit interleaving capability for minimization of soft error rate , 2018, Microelectron. J..

[6]  Jan M. Rabaey,et al.  Low Power Design Essentials , 2009, Series on Integrated Circuits and Systems.

[7]  Sied Mehdi Fakhraie,et al.  An 8T Low-Voltage and Low-Leakage Half-Selection Disturb-Free SRAM Using Bulk-CMOS and FinFETs , 2014, IEEE Transactions on Electron Devices.

[8]  S. Chouhan,et al.  A robust, ultra low-power, data-dependent-power-supplied 11T SRAM cell with expanded read/write stabilities for internet-of-things applications , 2018, Analog Integrated Circuits and Signal Processing.

[9]  Neeta Pandey,et al.  A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Manoj Sachdev,et al.  A 290-mV, 3.34-MHz, 6T SRAM With pMOS Access Transistors and Boosted Wordline in 65-nm CMOS Technology , 2018, IEEE Journal of Solid-State Circuits.

[11]  Cristian Carmona,et al.  A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors , 2019, IEEE Transactions on Emerging Topics in Computing.

[12]  Sudeb Dasgupta,et al.  Compact Analytical Model to Extract Write Static Noise Margin (WSNM) for SRAM Cell at 45-nm and 65-nm Nodes , 2018, IEEE Transactions on Semiconductor Manufacturing.

[13]  K. Mistry,et al.  Low-k interconnect stack with metal-insulator-metal capacitors for 22nm high volume manufacturing , 2012, 2012 IEEE International Interconnect Technology Conference.

[14]  C. B. Kushwah,et al.  A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Mohammad Sharifkhani,et al.  A Subthreshold Symmetric SRAM Cell With High Read Stability , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[16]  David Blaauw,et al.  A 23-mW Face Recognition Processor with Mostly-Read 5T Memory in 40-nm CMOS , 2017, IEEE Journal of Solid-State Circuits.

[17]  Chua-Chin Wang,et al.  A Leakage Compensation Design for Low Supply Voltage SRAM , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Massoud Pedram,et al.  Internal write-back and read-before-write schemes to eliminate the disturbance to the half-selected cells in SRAMs , 2018, IET Circuits Devices Syst..

[19]  M. Torkelson,et al.  A low logic depth complex multiplier using distributed arithmetic , 2000, IEEE Journal of Solid-State Circuits.

[20]  Somayeh Timarchi,et al.  An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques , 2016, Circuits Syst. Signal Process..

[21]  Y. Nara,et al.  Scaling challenges of MOSFET for 32nm node and beyond , 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

[22]  Neeta Pandey,et al.  Pentavariate $V_{\mathrm{min}}$ Analysis of a Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write and Divided Bit-Line Read , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

[23]  Mohammad Gholami,et al.  Two Novel Ultra-Low-Power SRAM Cells with Separate Read and Write Path , 2019, Circuits Syst. Signal Process..

[24]  Mohd. Hasan,et al.  Low Leakage Fully Half-Select-Free Robust SRAM Cells With BTI Reliability Analysis , 2018, IEEE Transactions on Device and Materials Reliability.

[25]  Mohd. Hasan,et al.  Pseudo differential multi-cell upset immune robust SRAM cell for ultra-low power applications , 2018 .

[26]  Mohammed Ismail,et al.  Design Methodologies for Yield Enhancement and Power Efficiency in SRAM-Based SoCs , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[27]  Behzad Ebrahimi,et al.  A robust and low power 7T SRAM cell design , 2015, 2015 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS).