A Low Complexity and High Throughput MIMO Detection VLSI Design for MIMO-OFDM Systems

This paper presents a linear Minimum Mean Square Error (MMSE) MIMO Detector design for MIMO-OFDM systems based on Application-Specific Instrument- set Processor (ASIP). As part of the IEEE 802.11ac-compliant PHY baseband transceiver, the proposed MIMO detector offers low latency, high throughput with efficient resource utilization. The design has been synthesized with TSMC 40 nm CMOS technology, the logic gate count for each QRD engine is about 245 K gates. It is able to support 20/40/80MHz bandwidth and up to 4 spatial streams. Detection latency for 80 MHz VHT mode (234 data sub-carriers) is 750 ns.

[1]  Hartung-Gorre Verlag,et al.  Iterative MIMO Decoding: Algorithms and VLSI Implementation Aspects , 2009 .

[2]  Ji-Hwan Yoon,et al.  A low-complexity composite QR decomposition architecture for MIMO detector , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

[3]  Carl Christian Sten Dominic Senning.  Energy Efficient VLSI Circuits for MIMO-WLAN , 2014 .

[4]  Peter Jan Lüthi,et al.  VLSI Circuits for MIMO Preprocessing , 2009 .

[5]  A. Burg,et al.  Matrix Decomposition Architecture for MIMO Systems: Design and Implementation Trade-offs , 2007, 2007 Conference Record of the Forty-First Asilomar Conference on Signals, Systems and Computers.

[6]  Christoph Studer,et al.  Iterative MIMO decoding , 2009 .

[7]  Babak Daneshrad,et al.  A Practical, Hardware Friendly MMSE Detector for MIMO-OFDM-Based Systems , 2008, EURASIP J. Adv. Signal Process..

[8]  Bilal Syed Hussain,et al.  Flexible, Efficient Multimode MIMO Detection by Using Reconfigurable ASIP , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Andreas Peter Burg,et al.  Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[10]  Pei-Yun Tsai,et al.  Efficient Implementation of QR Decomposition for Gigabit MIMO-OFDM Systems , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[11]  Rainer Leupers,et al.  A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[12]  Sébastien Roy,et al.  An efficient regular matrix inversion circuit architecture for MIMO processing , 2006, 2006 IEEE International Symposium on Circuits and Systems.