High-performance standard cell library and modeling technique for differential advanced bipolar current tree logic

A high-performance standard cell library for the Tektronix advanced bipolar process GST1 has been developed. The library is targeted for the 250-MIPS (million instructions per second) fast reduced instruction set computer (FRISC) project. The GST1 devices have a minimal emitter size of 0.6 mu m*2.4 mu m and a maximum f/sub t/ of 15.5 GHz. By combining advanced bipolar technology and high-speed differential logic, gate propagation delays of 90 ps can be achieved at a power dissipation of 70 mW. The fastest buffers/inverters have a propagation delay of only 68 ps. A 32-b ALU (arithmetic and logic unit) partitioned into four slices can perform an addition in 3 ns using differential standard cells with improved emitter-follower outputs and fast differential I/O drivers. A modeling technique for high-speed differential current tree logic is introduced. The technique gives accurate timing information and models the transient behavior of current trees. >

[1]  Takeshi Yamaguchi,et al.  A dual 4-bit, 1.5 Gs/s analog to digital converter , 1988, Proceedings of the 1988 Bipolar Circuits and Technology Meeting,.

[2]  L. Heller,et al.  Cascode voltage switch logic: A differential CMOS logic family , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[3]  V. E. Garuts,et al.  Process and device performance of a high-speed double poly-Si bipolar technology using borosenic-poly process with coupling-base implant , 1988 .

[4]  S. Konaka,et al.  43-ps 5.2-GHz macrocell array LSIs , 1988 .

[5]  A. Gupta,et al.  Design Aids for the Simulation of Bipolar Gate Arrays , 1983, 20th Design Automation Conference Proceedings.

[6]  Shoichi Shimizu,et al.  An ECL-compatible GaAs SCFL design method , 1990 .

[7]  Daniel G. Saab,et al.  Switch-Level Logic Simulation of Digital Bipolar Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  John F. McDonald,et al.  Key components of the fast reduced instruction set computer (FRISC) employing advanced bipolar differential logic and wafer scale multichip packaging , 1988, Proceedings of the 1988 Bipolar Circuits and Technology Meeting,.

[9]  R.L. Treadway.  DC analysis of current mode logic , 1989, IEEE Circuits and Devices Magazine.

[10]  Ernst G. Ulrich.  Exclusive simulation of activity in digital networks , 1969, CACM.

[11]  G. Eiden,et al.  High-speed polysilicon emitter—base bipolar transistor , 1986, IEEE Electron Device Letters.

[12]  H. Ichino,et al.  Super self-aligned process technology (SST) and its applications , 1988, Proceedings of the 1988 Bipolar Circuits and Technology Meeting,.

[13]  W. Fang.  Accurate analytical delay expressions for ECL and CML circuits and their applications to optimizing high-speed bipolar circuits , 1990 .

[14]  Catherine Mallardeau,et al.  A 10 K-gate 950 MHz CML demonstrator circuit made with a 1- mu m trench-isolated bipolar silicon technology , 1989 .