A Mixed-Signal Test Bus and Analog BIST with 'Unlimited' Time and Voltage Resolution

This paper describes a test bus suitable for conveying analog and digital signals to/from an unlimited number of circuit nodes with almost unlimited time or voltage resolution, in contrast to analog buses which are unlimited only in voltage resolution. A strategy is described that extends a silicon-proven approach for BIST of jitter and delays in PLLs, to BIST of 'random' analog functions. A variety of stimulus and response capture approaches is used to translate analog parameters from any number of circuit nodes, addressed by a P1687-like scheme, into digital waveforms conveyed via digitally under sampled serial bit streams or analog over sampled sigma-delta bit streams, to shared RTL-synthesized measurement circuits. Examples are presented for diverse circuit parameters.

[1]  Aubin Roy,et al.  High accuracy stimulus generation for A/D converter BIST , 2002, Proceedings. International Test Conference.

[2]  B. Kaminska,et al.  T-BIST: A built-in self-test for analog circuits based on parameter translation , 1993, Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS).

[3]  John McDermid.  Limited access testing: IEEE 1149.4-instrumentation and methods , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[4]  Aubin Roy,et al.  A selt-testing BOST for high-frequency PLLs, DLLs, and SerDes , 2007, 2007 IEEE International Test Conference.

[5]  Aubin Roy,et al.  Structural tests for jitter tolerance in SerDes receivers , 2005, ITC.

[6]  Diego Vázquez,et al.  A low-cost digital frequency testing approach for mixed-signal devices using SigmaDelta modulation , 2005, Microelectron. J..

[7]  Gordon W. Roberts,et al.  Test and evaluation of multiple embedded mixed-signal test cores , 2002, Proceedings. International Test Conference.

[8]  Stephen K. Sunter,et al.  Experiences with parametric BIST for production testing PLLs with picosecond precision , 2010, 2010 IEEE International Test Conference.

[9]  Guido Gronthoud,et al.  Analog Test Bus Infrastructure for RF/AMS Modules in Core-Based Design , 2008, 2008 13th European Test Symposium.

[10]  Florence Azaïs,et al.  On-chip analog output response compaction , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[11]  Behzad Razavi,et al.  Design techniques for high-speed, high-resolution comparators , 1992 .

[12]  Luigi Carro,et al.  Ultimate low cost analog BIST , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[13]  Foster F. Dai,et al.  Automatic linearity and frequency response tests with built-in pattern generator and analyzer , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  Gordon W. Roberts,et al.  A BIST scheme for an SNR test of a sigma-delta ADC , 1993, Proceedings of IEEE International Test Conference - (ITC).

[15]  Frank Poehl,et al.  Production test challenges for highly integrated mobile phone SOCs — A case study , 2010, 2010 15th IEEE European Test Symposium.

[16]  Salvador Mir,et al.  ABILBO: Analog BuILt-in block observer , 1996, Proceedings of International Conference on Computer Aided Design.

[17]  M. Nicolaidis,et al.  AC/DC BIST for testing analog circuits , 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

[18]  Jacob A. Abraham,et al.  Analog Testing with Time Response Parameters , 1996, IEEE Des. Test Comput..

[19]  Gordon W. Roberts,et al.  A stand-alone integrated test core for time and frequency domain measurements , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[20]  A.V. Oppenheim,et al.  The importance of phase in signals , 1980, Proceedings of the IEEE.

[21]  Aubin Roy,et al.  Noise-Insensitive Digital BIST for any PLL or DLL , 2008, J. Electron. Test..

[22]  Christian Dufaza,et al.  A BIST-DFT technique for DC test of analog modules , 1996, J. Electron. Test..

[23]  Karim Arabi,et al.  Design for testability of integrated operational amplifiers using oscillation-test strategy , 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

[24]  Bozena Kaminska,et al.  Frequency-based BIST for analog circuit testing , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[25]  Kari Halonen,et al.  A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters , 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).