High-speed, area efficient VLSI architecture of wallace-tree multiplier for DSP-applications

Most modern arithmetic processors are built with architectures that have been well-established in the literature, with many of the latest innovations devoted to special logic circuits and the use of advanced technologies. Specifically, the design of multipliers is critical in digital signal processing applications, where a high number of multiplications are required. We have minimized the number of adders by introducing different compressors. Binary counter property has been merged with the compressor property to develop high order compressors such as 5-3 and 7-3 compressors.

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