A compact 0.3–10 GHz broadband stacked amplifier in 65nm standard CMOS

This work presents the design and implementation of a fully integrated broadband medium power stacked amplifier in 65 nm bulk CMOS. The amplifier topology utilizes three NMOS stack and three PMOS stack to increase the output voltage swing along with the output impedance. The load impedance is further optimized with a resistive feedback which not only results in broadband operation but also avoids a lossy broadband output matching network which reduces area significantly. Further, small interstage peaking inductors are employed to peak the parasitics capacitances that limit the broadband operation. The proposed amplifier shows a measured peak saturated output power from 13 dBm to 8.5 dBm and a P1dB of 7 dBm to 4 dBm from 0.3 GHz to 10 GHz. The measured gain is 9 dB with a gain ripple of ±1.5 dB in the entire frequency range, yielding a fractional bandwidth of 188%. The measured load-pull -1 dB, -2 dB output power contours verify the optimum impedance around 50 Ω. The active chip area is only 0.44mm2.

[1]  V. Puyal,et al.  A broad-band active frequency doubler operating up to 120 GHz , 2005, European Gallium Arsenide and Other Semiconductor Application Symposium, GAAS 2005.

[2]  Zhang Wei,et al.  An ultra-wideband Darlington low noise amplifier design based on SiGe HBT , 2008, 2008 International Conference on Microwave and Millimeter Wave Technology.

[3]  Jinho Jeong,et al.  A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS , 2010, IEEE Transactions on Microwave Theory and Techniques.

[4]  K.W. Kobayashi Linearized Darlington Cascode Amplifier Employing GaAs PHEMT and GaN HEMT Technologies , 2007, IEEE Journal of Solid-State Circuits.

[5]  Behzad Razavi Prospects of CMOS technology for high-speed optical communication circuits , 2001 .

[6]  Shuhei Amakawa,et al.  Design of CMOS inverter-based output buffers adapting the cherry-hooper broadbanding technique , 2009, 2009 European Conference on Circuit Theory and Design.

[7]  Chao Lu,et al.  Linearization of CMOS Broadband Power Amplifiers Through Combined Multigated Transistors and Capacitance Compensation , 2007, IEEE Transactions on Microwave Theory and Techniques.

[8]  Chin-Yung Chiu,et al.  A fully integrated multi-standard power amplifier in 0.18 /spl mu/m CMOS for IEEE 802.11 a/b/g WLANs , 2005, 48th Midwest Symposium on Circuits and Systems, 2005..

[9]  A. Vasylyev,et al.  Ultra-broadband 20.5–31 GHz monolithically-integrated CMOS power amplifier , 2005 .

[10]  Chun-Lin Ko,et al.  A 4.2-mW 6-dB Gain 5–65-GHz Gate-Pumped Down-Conversion Mixer Using Darlington Cell for 60-GHz CMOS Receiver , 2013, IEEE Transactions on Microwave Theory and Techniques.

[11]  F. Aryanfar,et al.  A Broadband Stacked Power Amplifier in 45-nm CMOS SOI Technology , 2013, IEEE Journal of Solid-State Circuits.

[12]  Kuo-Liang Deng,et al.  Design and analysis of DC-to-14-GHz and 22-GHz CMOS cascode , 2004 .