Sustainable and Reliable On-Chip Wireless Communication Infrastructure for Massive Multi-core Systems

The Network-on-Chip paradigm has emerged as an enabling methodology to integrate high number of functional cores on a single die. However, the metal interconnect based multi-hop on-chip networks result in high latency and energy dissipation in data transfer. In order to alleviate these problems several emerging interconnect technologies have been proposed. Wireless NoC architectures are shown to outperform the wired counterparts by several orders of magnitude in energy dissipation while achieving higher data transfer rates. However, reliability of the wireless links along with the metal NoC interconnects are known to be a major concern in the future technology nodes. Powerful error control codes based on product codes can enhance the resilience of the wireless channels making the overall NoC more reliable. A unified error control mechanism to enhance the resilience to transient errors of the wireless links as well as the wireline links is presented. This chapter showcases the achievable performance benefits of the wireless NoC architectures while still maintaining acceptable robustness to transient errors.

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