The PAL System - A Parallel Algorith Design System for VLSI Based Array Architectures

The parallel algorithm laboratory (PAL) under development at Michigan State University is a system to aid in the top-down design of asynchronous parallel algorithms to be implemented on a VLSI-based array architecture. At each step in the design of an algorithm, information is used to parameterize the computational needs of the current array architectures that efficiently support execution of the algorithm. Therefore, when the design process is terminated, the user will have not only a graphical specification of the algorithm, but also a set of functional requirements that the VLSI configuration must support in order for the algorithm to run efficiently. Here the process of matching an algorithm to a target class of architecture is formally defined. The class of machines and algorithms that are to be matched are described. Next, the extent to which the proposed PAL system supports both the design and matching process for an algorithm are discussed. 4 references.