A genetic approach to automatic bias generation for biased random instruction generation
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Jongshin Shin | E.M. Rudnick | M. Abadir | M. Bose | T. Dukes | M. Abadir | E. Rudnick | Mrinal Bose | M. Bose | Jong-Ryeol Shin | T. Dukes | Jongshin Shin | Elizabeth M. Rudnick | Todd Dukes
[1] Elizabeth M. Rudnick,et al. A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors , 2000, J. Electron. Test..
[2] Laurent Fournier,et al. Developing an architecture validation suite: application to the PowerPC architecture , 1999, DAC '99.
[3] Sharad Malik,et al. Toward formalizing a validation methodology using simulation coverage , 1997, DAC.
[4] Aharon Aharon,et al. Verification of the IBM RISC System/6000 by a Dynamic Biased Pseudo-Random Test Program Generator , 1991, IBM Syst. J..
[5] Carl Ramey,et al. Functional verification of a multiple-issue, out-of-order, superscalar Alpha processor-the DEC Alpha 21264 microprocessor , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[6] Daniel Geist,et al. AVPGEN-A test generator for architecture verification , 1995, IEEE Trans. Very Large Scale Integr. Syst..
[7] David E. Goldberg,et al. Genetic Algorithms in Search Optimization and Machine Learning , 1988 .
[8] Alan Hartman,et al. A study in coverage-driven test generation , 1999, DAC '99.