Replica compensated linear regulators for supply-regulated phase-locked loops
暂无分享,去创建一个
E. Alon | J. Kim | S. Pamarti | K. Chang | M. Horowitz
[1] J.G. Maneatis,et al. Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
[2] W.J. Dally,et al. Low-power area-efficient high-speed I/O circuit techniques , 2000, IEEE Journal of Solid-State Circuits.
[3] C. Piguet,et al. A 320 MHz, 1.5 mW at 1.35 V CMOS PLL for microprocessor clock generation , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
[4] M. Horowitz,et al. Circuits and techniques for high-resolution measurement of on-chip power supply noise , 2004, IEEE Journal of Solid-State Circuits.
[5] M. Horowitz,et al. Clocking and circuit design for a parallel I/O on a first-generation CELL processor , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
[6] M. Horowitz,et al. Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).
[7] Bram Nauta,et al. Embedded 5 V-to-3.3 V voltage regulator for supplying digital IC's in 3.3 V CMOS technology , 1998, IEEE J. Solid State Circuits.
[8] Chih-Kong Ken Yang,et al. Jitter optimization based on phase-locked loop design parameters , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[9] Ali Hajimiri,et al. A general theory of phase noise in electrical oscillators , 1998 .
[10] J. Wei,et al. A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).