Layout decomposition of self-aligned double patterning for 2D random logic patterning
暂无分享,去创建一个
[1] Andrew B. Kahng,et al. Layout decomposition for double patterning lithography , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.
[2] Kanak Agarwal. Frequency domain decomposition of layouts for double dipole lithography , 2010, Design Automation Conference.
[3] Kun Yuan,et al. Layout Decomposition for Triple Patterning Lithography , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[4] Andrew B. Kahng,et al. Timing Yield-Aware Color Reassignment and Detailed Placement Perturbation for Bimodal CD Distribution in Double Patterning Lithography , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[5] Jerry Liu,et al. Advanced self-aligned double patterning development for sub-30-nm DRAM manufacturing , 2009, Advanced Lithography.
[6] Kun Yuan,et al. A new graph-theoretic, multi-objective layout decomposition framework for Double Patterning Lithography , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).
[7] David Z. Pan,et al. Double patterning technology friendly detailed routing , 2008, ICCAD 2008.
[8] David Z. Pan,et al. Flexible 2D layout decomposition framework for spacer-type double pattering lithography , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).
[9] Yunfei Deng,et al. Decomposition strategies for self-aligned double patterning , 2010, Advanced Lithography.
[10] Yi-Shiang Chang,et al. Full area pattern decomposition of self-aligned double patterning for 30nm node NAND FLASH process , 2010, Advanced Lithography.
[11] Christopher Cork,et al. Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows , 2010, Advanced Lithography.
[12] Lars W. Liebmann,et al. Taming the final frontier of optical lithography: design for sub-resolution patterning , 2010, Advanced Lithography.
[13] Kun Yuan,et al. Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.