100 Gbit/s multiplexing and demultiplexing IC operations in InP HEMT technology

The 100 Gbit/s multiplexing operation of a selector IC and the demultiplexing operation of a D-type flip-flop (D-FF) using a production-level 0.1 /spl mu/m-gate InP HEMT IC technology is described. Eye-openings of the selector IC at 100 Gbit/s and its error-free operation were confirmed using a test chip containing the selector and the D-FF. To the authors' best knowledge, this is the first report of 100 Gbit/s operation of a transistor-based integrated circuit.

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