Information-theoretic bounds on average signal transition activity [VLSI systems]

Transitions on high-capacitance buses in very large scale integration systems result in considerable system power dissipation. Therefore, various coding schemes have been proposed in the literature to encode the input signal in order to reduce the number of transitions. In this paper, we derive lower and upper bounds on the average signal transition activity via an information-theoretic approach, in which symbols generated by a process (possibly correlated) with entropy rate H are coded with an average of R bits per symbol. The bounds are asymptotically achievable if the process is stationary and ergodic. We also present a coding algorithm based on the Lempel-Ziv data-compression algorithm to achieve the bounds. Bounds are also obtained on the expected number of ones (or zeros). These results are applied to determine the activity-reducing efficiency of different coding algorithms such as, entropy coding, transition signaling, and bus-invert coding, and determine the lower bound on the power-delay product given H and R. Two examples are provided where transition activity within 4% and 9% of the lower bound is achieved when blocks of eight symbols and 13 symbols, respectively, are coded at a time.

[1]  Luca Benini,et al.  Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems , 1997, Proceedings Great Lakes Symposium on VLSI.

[2]  Abraham Lempel,et al.  A universal algorithm for sequential data compression , 1977, IEEE Trans. Inf. Theory.

[3]  Naresh R. Shanbhag Lower bounds on power dissipation for DSP algorithms , 1996, ISLPED.

[4]  Radu Marculescu,et al.  Information theoretic measures for power analysis [logic design] , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Mircea R. Stan,et al.  Coding a terminated bus for low power , 1995, Proceedings. Fifth Great Lakes Symposium on VLSI.

[6]  Naresh R. Shanbhag,et al.  A Mathematical Basis For Power-Reduction In Digital VLSI Systems , 1997 .

[7]  Terry A. Welch,et al.  A Technique for High-Performance Data Compression , 1984, Computer.

[8]  Farid N. Najm,et al.  Towards a high-level power estimation capability , 1995, ISLPED '95.

[9]  Mircea R. Stan,et al.  Bus-invert coding for low-power I/O , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[10]  Mircea R. Stan,et al.  Limited-weight codes for low-power I/O , 1994 .

[11]  Thomas M. Cover,et al.  Elements of Information Theory , 2005 .

[12]  Naresh R. Shanbhag Lower bounds on power-dissipation for DSP algorithms , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

[13]  R. Marculescu,et al.  Switching Activity Analysis Considering Spatioternporal Correlations , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[14]  Mircea R. Stan,et al.  Two-dimensional codes for low power , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

[15]  M. Horowitz,et al.  Low-power digital design , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.

[16]  Radu Marculescu,et al.  Switching activity analysis considering spatiotemporal correlations , 1994, ICCAD.

[17]  Keshab K. Parhi,et al.  Algorithm transformation techniques for concurrent processors , 1989, Proc. IEEE.

[18]  Naresh R. Shanbhag A fundamental basis for power-reduction in VLSI circuits , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[19]  Farid N. Najm,et al.  Towards a high-level power estimation capability [digital ICs] , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Kurt Keutzer,et al.  On average power dissipation and random pattern testability of CMOS combinational logic networks , 1992, ICCAD.

[21]  Ibrahim N. Hajj,et al.  Switch-Level Timing Simulation of Mos VLSI Circuits , 1988 .

[22]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[23]  Anantha P. Chandrakasan,et al.  Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.

[24]  Chi-Ying Tsui,et al.  Saving power in the control path of embedded processors , 1994, IEEE Design & Test of Computers.

[25]  Naresh R. Shanbhag,et al.  A coding framework for low-power address and data busses , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[26]  R. Marculescu,et al.  Information theoretic measures for power analysis : Low power design , 1996 .

[27]  Naresh R. Shanbhag,et al.  Coding for low-power address and data busses: a source-coding framework and applications , 1998, Proceedings Eleventh International Conference on VLSI Design.

[28]  Massoud Pedram,et al.  An approach for multilevel logic optimization targeting low power , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[29]  Sungpack Hong,et al.  Decomposition of Bus-Invert Coding for Low-Power I/O , 2000, J. Circuits Syst. Comput..