Simulation of enhanced injection split gate flash EEPROM device programming
暂无分享,去创建一个
The recent trend of mixed technology processes for versatile chip design has prompted the need for 5 V only CMOS compatible non-volatile memory devices. However, for high-speed applications flash EEPROM devices are generally used but often require external power supplies for the writing cycles. The High Injection MOS (HIMOS) cell can be programmed at high speed with a 5 V power supply and so is promising for low-density high-speed applications where only a single power supply is available. To aid in the design and optimisation of the HIMOS device a 2-D numerical device simulator HFIELDS has been adapted to simulate the hot-electron injection currents. This is the first time that numerical simulations of a split gate type flash EEPROM device have been reported and comparisons with measured data show good agreement.
[1] L. Ravazzi,et al. Complete transient simulation of flash EEPROM devices , 1990, International Technical Digest on Electron Devices.
[2] G. Groeseneken,et al. Study of the enhanced hot-electron injection in split-gate transistor structures , 1990, ESSDERC '90: 20th European Solid State Device Research Conference.