CAD at the design-manufacturing interface
暂无分享,去创建一个
Wojciech Maly | Witold A. Pleskacz | Pranab K. Nag | Jitendra Khare | Hans T. Heineken | Charles H. Ouyang
[1] Witold A. Pleskacz,et al. SENSAT-a practical tool for estimation of the IC layout sensitivity to spot defects , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.
[2] Wojciech Maly,et al. Design for manufacturability in submicron domain , 1996, Proceedings of International Conference on Computer Aided Design.
[3] Wojciech Maly,et al. Extraction of critical areas for opens in large VLSI circuits , 1996, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
[4] Wojciech Maly,et al. Yield estimation model for VLSI artwork evaluation , 1983 .
[5] J. McVittie,et al. Thin-oxide damage from gate charging during plasma processing , 1992, IEEE Electron Device Letters.
[6] Charles H. Stapper. Yield Model for Fault Clusters Within Integrated Circuits , 1984, IBM J. Res. Dev..
[7] Wojciech Maly. The future of IC design, testing, and manufacturing , 1996, IEEE Des. Test Comput..
[8] Charles H. Stapper,et al. Modeling of Defects in Integrated Circuit Photolithographic Patterns , 1984, IBM J. Res. Dev..
[9] Massoud Pedram,et al. Interconnection length estimation for optimized standard cell layouts , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[10] Wojciech Maly,et al. Critical area analysis for design-based yield improvement of VLSI circuits , 1995 .
[11] A. V. Ferris-Prabhu,et al. Modeling the critical area in yield forecasts , 1985 .
[12] Wojciech Maly,et al. Yield loss forecasting in the early phases of the VLSI design process , 1996, Proceedings of Custom Integrated Circuits Conference.
[13] Anthony J. Walton,et al. Yield prediction by sampling with the EYES tool , 1996, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
[14] Wojciech Maly,et al. Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs , 1996, ICCAD 1996.
[15] Wojciech Maly,et al. Manufacturability analysis environment-MAPEX , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.
[16] Wojciech Maly,et al. Computer-aided design for VLSI circuit manufacturability , 1990, Proc. IEEE.
[17] Wojciech Maly,et al. Detection of an antenna effect in VLSI designs , 1996, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
[18] Wojciech Maly,et al. Hierarchical extraction of critical area for shorts in very large ICs , 1995, Proceedings of International Workshop on Defect and Fault Tolerance in VLSI.