Approaching Miscorrection-Free Performance of Product Codes With Anchor Decoding

Product codes (PCs) protect a 2-D array of bits using short component codes. Assuming transmission over the binary symmetric channel, the decoding is commonly performed by iteratively applying bounded-distance decoding to the component codes. For this coding scheme, undetected errors in the component decoding—also known as miscorrections—significantly degrade the performance. In this paper, we propose a novel iterative decoding algorithm for PCs which can detect and avoid most miscorrections. The algorithm can also be used to decode many recently proposed classes of generalized PCs, such as staircase, braided, and half-product codes. Depending on the component code parameters, our algorithm significantly outperforms the conventional iterative decoding method. As an example, for double-error-correcting Bose–Chaudhuri–Hocquenghem component codes, the net coding gain can be increased by up to 0.4 dB. Moreover, the error floor can be lowered by orders of magnitude, up to the point where the decoder performs virtually identical to a genie-aided decoder that avoids all miscorrections. We also discuss post-processing techniques that can be used to reduce the error floor even further.

[1]  Frank R. Kschischang,et al.  Decoding analysis accounting for mis-corrections for spatially-coupled split-component codes , 2016, 2016 IEEE International Symposium on Information Theory (ISIT).

[2]  Henry D. Pfister,et al.  Density Evolution for Deterministic Generalized Product Codes on the Binary Erasure Channel at High Rates , 2015, IEEE Transactions on Information Theory.

[3]  Masao Kasahara,et al.  Modified product codes , 1984, IEEE Trans. Inf. Theory.

[4]  Paul H. Siegel,et al.  On the asymptotic performance of iterative decoders for product codes , 2005, Proceedings. International Symposium on Information Theory, 2005. ISIT 2005..

[5]  H.C. Chang,et al.  A Reed-Solomon Product-Code (RS-PC) decoder for DVD applications , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[6]  Jørn Justesen,et al.  Performance of Product Codes and Related Structures with Iterated Decoding , 2011, IEEE Transactions on Communications.

[7]  Omid Etesami,et al.  Irregular product codes , 2012, 2012 IEEE Information Theory Workshop.

[8]  Michael Lentmaier,et al.  Braided Block Codes , 2009, IEEE Transactions on Information Theory.

[9]  P. A. Wintz,et al.  Error Free Coding , 1973 .

[10]  Alexandre Graell i Amat,et al.  On parameter optimization for staircase codes , 2015, 2015 Optical Fiber Communications Conference and Exhibition (OFC).

[11]  Henry D. Pfister,et al.  Approaching capacity at high rates with iterative hard-decision decoding , 2012, 2012 IEEE International Symposium on Information Theory Proceedings.

[12]  Robert J. McEliece,et al.  On the decoder error probability for Reed-Solomon codes , 1986, IEEE Trans. Inf. Theory.

[13]  Henry D. Pfister,et al.  Iterative hard-decision decoding of braided BCH codes for high-speed optical communication , 2013, 2013 IEEE Global Communications Conference (GLOBECOM).

[14]  Martin Bossert,et al.  On Iterative Soft-Decision Decoding of Linear Binary Block Codes and Product Codes , 1998, IEEE J. Sel. Areas Commun..

[15]  Michael Scholten,et al.  Continuously-interleaved BCH (CI-BCH) FEC delivers best in class NECG for 40G and 100G metro applications , 2010, 2010 Conference on Optical Fiber Communication (OFC/NFOEC), collocated National Fiber Optic Engineers Conference.

[16]  Warren J. Gross,et al.  Stall pattern avoidance in polynomial product codes , 2016, 2016 IEEE Global Conference on Signal and Information Processing (GlobalSIP).

[17]  Frank R. Kschischang,et al.  Spatially Coupled Split-Component Codes With Iterative Algebraic Decoding , 2015, IEEE Transactions on Information Theory.

[18]  Babak Falsafi,et al.  Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[19]  Norman Abramson,et al.  Cascade Decoding of Cyclic Product Codes , 1968 .

[20]  Henry D. Pfister,et al.  Miscorrection-free Decoding of Staircase Codes , 2017, 2017 European Conference on Optical Communication (ECOC).

[21]  François Leduc-Primeau,et al.  A 9.52 dB NCG FEC Scheme and 162 b/Cycle Low-Complexity Product Decoder Architecture , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

[22]  C. B. Shung,et al.  A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications , 1998 .

[23]  Hannes Bartz,et al.  Improved decoding and error floor analysis of staircase codes , 2019, Des. Codes Cryptogr..

[24]  Chaitali Chakrabarti,et al.  Product Code Schemes for Error Correction in MLC NAND Flash Memories , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[25]  Frank R. Kschischang,et al.  Staircase Codes With 6% to 33% Overhead , 2014, Journal of Lightwave Technology.

[26]  Neal Zierler,et al.  Two-Error Correcting Bose-Chaudhuri Codes are Quasi-Perfect , 1960, Inf. Control..

[27]  Ramesh Pyndiah,et al.  Near-optimum decoding of product codes: block turbo codes , 1998, IEEE Trans. Commun..

[28]  Henry D. Pfister,et al.  Symmetric product codes , 2015, 2015 Information Theory and Applications Workshop (ITA).

[29]  J. Justesen,et al.  Analysis of Iterated Hard Decision Decoding of Product Codes with Reed-Solomon Component Codes , 2007, 2007 IEEE Information Theory Workshop.

[30]  Warren J. Gross,et al.  A 9.52 dB NCG FEC Scheme and 162 b/Cycle Low-Complexity Product Decoder Architecture , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

[31]  Jørn Justesen,et al.  Error correcting coding for OTN , 2010, IEEE Communications Magazine.

[32]  Seiichi Mita,et al.  A Novel Error-Correcting System Based on Product Codes for Future Magnetic Recording Channels , 2011, IEEE Transactions on Magnetics.

[33]  Benjamin Peter Smith,et al.  Error-correcting Codes for Fibre-optic Communication Systems , 2012 .

[34]  Frank R. Kschischang,et al.  Staircase Codes: FEC for 100 Gb/s OTN , 2012, Journal of Lightwave Technology.

[35]  Henry D. Pfister,et al.  Density evolution and error floor analysis for staircase and braided codes , 2016, 2016 Optical Fiber Communications Conference and Exhibition (OFC).

[36]  Thomas P. Parnell,et al.  Improving the error-floor performance of binary half-product codes , 2016, 2016 International Symposium on Information Theory and Its Applications (ISITA).