A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider

The adoption of dynamic dividers in CMOS phase-locked loops for multigigahertz applications allows to reduce the power consumption substantially without impairing the phase noise and the power supply sensitivity of the phase-locked loop (PLL). A 5-GHz frequency synthesizer integrated in a 0.25-/spl mu/m CMOS technology demonstrates a total power consumption of 13.5 mW. The frequency divider combines the conventional and the extended true-single-phase-clock logics. The oscillator employs a rail-to-rail topology in order to ensure a proper divider function. This PLL intended for wireless LAN applications can synthesize frequencies between 5.14 and 5.70 GHz in steps of 20 MHz. The reference spurs at 10-MHz offset are as low as -70 dBc and the phase noise is lower than -116 dBc/Hz at 1 MHz over the whole tuning range.

[1]  Christer Svensson,et al.  High-speed CMOS circuit technique , 1989 .

[2]  M. Ipek,et al.  A multi standard single-chip transceiver covering 5.15 to 5.85GHz , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[3]  Herschel A. Ainspan,et al.  A fully-integrated 5-GHz frequency synthesizer in SiGe BiCMOS , 1999, Proceedings of the 1999 Bipolar/BiCMOS Circuits and Technology Meeting (Cat. No.99CH37024).

[4]  B.-U. H. Klepser,et al.  A 10 GHz SiGe BiCMOS phase-locked-loop frequency synthesizer , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[5]  Chih-Ming Hung,et al.  A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop , 2002, IEEE J. Solid State Circuits.

[6]  N. Krishnapura,et al.  A 5.3-GHz programmable divider for HiPerLAN in 0.25-/spl mu/m CMOS , 2000, IEEE Journal of Solid-State Circuits.

[7]  H.R. Rategh,et al.  A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver , 2000, IEEE Journal of Solid-State Circuits.

[8]  P.R. Gray,et al.  A 1.4 GHz differential low-noise CMOS frequency synthesizer using a wideband PLL architecture , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[9]  Howard C. Luong,et al.  A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM receivers , 2001 .

[10]  T.H. Lee,et al.  Comments on "Design issues in CMOS differential LC oscillators" [and reply] , 2000, IEEE Journal of Solid-State Circuits.

[11]  Shen-Iuan Liu,et al.  Low-Voltage CMOS Frequency Synthesizer for , 2001 .

[12]  Salvatore Levantino,et al.  Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion , 2002, IEEE J. Solid State Circuits.

[13]  W.A.M. Van Noije,et al.  A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC) , 1999, IEEE J. Solid State Circuits.

[14]  Bruce A. Wooley,et al.  A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems , 2002 .

[15]  Venceslav F. Kroupa,et al.  Jitter and phase noise in frequency dividers , 2001, IEEE Trans. Instrum. Meas..

[16]  Qiuting Huang,et al.  Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks , 1996 .

[17]  B.-U.H. Klepser,et al.  A 5.7 GHz Hiperlan SiGe BiCMOS voltage-controlled oscillator and phase-locked-loop frequency synthesizer , 2001, 2001 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium (IEEE Cat. No.01CH37173).