NETRA: A parallel architecture for integrated vision systems. 1: Architecture and organization

Computer vision is regarded as one of the most complex and computationally intensive problems. An integrated vision system (IVS) is considered to be a system that uses vision algorithms from all levels of processing for a high level application (such as object recognition). A model of computation is presented for parallel processing for an IVS. Using the model, desired features and capabilities of a parallel architecture suitable for IVSs are derived. Then a multiprocessor architecture (called NETRA) is presented. This architecture is highly flexible without the use of complex interconnection schemes. The topology of NETRA is recursively defined and hence is easily scalable from small to large systems. Homogeneity of NETRA permits fault tolerance and graceful degradation under faults. It is a recursively defined tree-type hierarchical architecture where each of the leaf nodes consists of a cluster of processors connected with a programmable crossbar with selective broadcast capability to provide for desired flexibility. A qualitative evaluation of NETRA is presented. Then general schemes are described to map parallel algorithms onto NETRA. Algorithms are classified according to their communication requirements for parallel processing. An extensive analysis of inter-cluster communication strategies in NETRA is presented, and parameters affecting performance of parallel algorithms when mapped on NETRA are discussed. Finally, a methodology to evaluate performance of algorithms on NETRA is described.

[1]  Doug DeGroot,et al.  Partitioning Job Structures for SW-Banyan Networks , 1983, ICPP.

[2]  Steven L. Tanimoto,et al.  A hierarchical cellular logic for pyramid computers , 1984, J. Parallel Distributed Comput..

[3]  Luigi P. Cordella,et al.  An Analysis of Computational Cost in Image Processing: A Case Study , 1978, IEEE Transactions on Computers.

[4]  Azriel Rosenfeld,et al.  Image processing on MPP: 1 , 1982, Pattern Recognit..

[5]  Janak H. Patel Performance of Processor-Memory Interconnections for Multiprocessors , 1981, IEEE Transactions on Computers.

[6]  Jon Louis Bentley,et al.  Multidimensional divide-and-conquer , 1980, CACM.

[7]  H. T. Kung,et al.  Global operations on the CMU Warp machine , 1985 .

[8]  Jerry L. Potter Image processing on the massively parallel processor , 1983, Computer.

[9]  Alan Sussman,et al.  LINC : the link and interconnecting chip , 1984 .

[10]  Kenneth E. Batcher,et al.  Design of a Massively Parallel Processor , 1980, IEEE Transactions on Computers.

[11]  Howard Jay Siegel,et al.  PASM: A Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition , 1981, IEEE Transactions on Computers.

[12]  H. T. Kung,et al.  The Warp Computer: Architecture, Implementation, and Performance , 1987, IEEE Transactions on Computers.

[13]  Edward S. Davidson,et al.  Organization of Semiconductor Memories for Parallel-Pipelined Processors , 1977, IEEE Transactions on Computers.

[14]  Janak H. Patel,et al.  NETRA: A parallel architecture for integrated vision systems 2: Algorithms and performance evaluation , 1989 .

[15]  S. L. Tanimoto,et al.  A prototype pyramid machine for hierarchical cellular logic , 1987 .

[16]  Y.-W. Ma,et al.  The architecture of replica: A special-purpose computer system for active multi-sensory perception of 3-dimentional objects , 1984, ISCA '84.

[17]  Janak H. Patel,et al.  NETRA: an architecture for a large scale multiprocessor vision system , 1987 .

[18]  Narendra Ahuja,et al.  Multiprocessor Pyramid Architectures for Bottom-Up Image Analysis , 1984, IEEE Transactions on Pattern Analysis and Machine Intelligence.

[19]  W. A. Perkins INSPECTOR: A Computer Vision System that Learns to Inspect Parts , 1983, IEEE Transactions on Pattern Analysis and Machine Intelligence.

[20]  H. T. Kung,et al.  Warp as a machine for low-level vision , 1985, Proceedings. 1985 IEEE International Conference on Robotics and Automation.

[21]  Janak H. Patel,et al.  Point matching in a time sequence of stereo image pairs and its parallel implementation on a multiprocessor , 1989, [1989] Proceedings. Workshop on Visual Motion.

[22]  Michael J. B. Duff,et al.  Review of the CLIP image processing system , 1899, AFIPS National Computer Conference.

[23]  H. T. Kung Systolic algorithms for the CMU warp processor , 1984 .

[24]  FAYÉ A. BRIGGS,et al.  PM4—A reconfigurable multiprocessor system for pattern recognition and image processing , 1979, 1979 International Workshop on Managing Requirements Knowledge (MARK).

[25]  Howard Jay Siegel,et al.  PARTITIONING PERMUTATION NETWORKS : THE UNDERLYING THEORY , 2022 .

[26]  Janak H. Patel Analysis of Multiprocessors with Private Cache Memories , 1982, IEEE Transactions on Computers.