Highly testable and compact 1-out-of-n CMOS checkers

This paper presents an original concept for implementing 1-out-of-n (1/n) checkers (for any value of n), that are Totally Self Checking with respect to a set of realistic faults including also all resistive bridgings. With respect to other 1/n CMOS checkers, the proposed circuits feature higher self-testing capability and smaller silicon area. The advantages are obtained at the cost of a static power consumption that, however, compared with that typical of an alternate technique, will be shown to be not excessive and reducible by means of suitable techniques. In addition, as an example of the testability improvement achievable by means of the proposed implementations, the case of 1-out-of-3 will be explicitly treated.

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