A Routing Procedure for Mixed Array of Custom Macros and Standard Cells

Routing algorithms for multi- (more than 3) sided pin arrangements are presented. These algorithms are essential for layouts mixing standard cells with custom macros such as ROM, RAM, PLA and ALU. An extended layout model in which these algorithms are applied is also presented. An experimental result regarding the effect on block area with respect to cell height, obtained by comparing an extended model with a traditional model, is described.

[1]  David N. Deutsch A “DOGLEG” channel router , 1976, DAC 1976.

[2]  S. Horiguchi,et al.  An integrated modular and standard cell IC design method , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[3]  C. Erdelyi,et al.  A comparison of mixed gate array and custom IC design methods , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[4]  Akihiro Hashimoto,et al.  Wire routing by optimizing channel assignment within large apertures , 1971, DAC.

[5]  Koji Sato,et al.  MILD - A Cell-Based Layout System for MOS-LSI , 1981, 18th Design Automation Conference.

[6]  Ernst G. Ulrich,et al.  Clustering and linear placement , 1972, DAC '72.

[7]  Hidekazu Terai,et al.  Automatic Placement Algorithms for High Packing density VLSI , 1983, 20th Design Automation Conference Proceedings.

[8]  Hidekazu Terai,et al.  Combine and Top Down Block Placement Algorithm for Hierarchical Logic VLSI Layout , 1984, 21st Design Automation Conference Proceedings.