LILA: layout generation for iterative logic arrays

A CAD tool, LILA, that generates layouts of both one-dimensional and two-dimensional iterative logic arrays, described in VHDL or schematic structures, is presented. Such a tool is very important because in current industry, the generation of high density iterative logic arrays (such as data paths in microprocessors) is still mainly performed manually, and is a major bottleneck of the design. In LILA, interconnections between modules (i.e., cells) of the array do not need to be between adjacent modules and functions of modules of the array do not need to be identical. Regularity in module functions and interconnections between modules are automatically extracted by the tool. Based on interconnection wire length between modules, layouts of modules and interconnections are optimized in a single step. The signals in each array module are generated in such a way that signals in adjacent modules are perfectly aligned and connected by module abutments. As no global routing or channel routing between modules are necessary, the total layout area and propagation delay between modules are minimal. The proposed system is especially useful for data path modules, bit-level systolic arrays, storage devices, and many other regular structures, and has been actually implemented in a design environment. Extensive experiments have shown that the system has a very good performance and produces layouts of very high density. The tool takes about 1.6 CPU seconds to generate an eight-by-eight array divider on a SUN SPARCstation II. >

[1]  Gwo-Dong Chen,et al.  An intelligent component database for behavioral synthesis , 1991, DAC '90.

[2]  Q. Wu,et al.  BLACK/CLAD: a layout synthesis tool for combinational blocks from behavioral HDL descriptions , 1992, [1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems.

[3]  Takao Uehara,et al.  Optimal Layout of CMOS Functional Arrays , 1978, 16th Design Automation Conference.

[4]  Charles J. Poirier.  Excellerator: custom CMOS leaf cell layout generator , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Hugo De Man,et al.  A data path layout assembler for high performance DSP circuits , 1991, DAC '90.

[6]  John P. Hayes,et al.  An Array Layout Methodology for VLSI Circuits , 1986, IEEE Transactions on Computers.

[7]  Edmund M. Clarke,et al.  Escher-a geometrical layout system for recursively defined circuits , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Donald G. Baltus,et al.  SOLO: a generator of efficient layouts from optimized MOS circuit schematics , 1988, DAC '88.

[9]  Q. Wu,et al.  Layout synthesis of combinational blocks from behavioral hardware descriptions , 1992, [1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit.

[10]  Charles M. Fiduccia,et al.  A linear-time heuristic for improving network partitions , 1988, 25 years of DAC.

[11]  Ron Y. Pinter,et al.  Optimal Chaining of CMOS Transistors in a Functional Cell , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Daniel G. Schweikert,et al.  LTX - a system for the directed automatic design of LSI circuits , 1976, DAC.

[13]  Joseph Y.-T. Leung,et al.  An Optimal Solution for the Channel-Assignment Problem , 1979, IEEE Transactions on Computers.

[14]  Uehara,et al.  Optimal Layout of CMOS Functional Arrays , 1981 .

[15]  P. W. Kollaritsch,et al.  TOPOLOGIZER: An Expert System Translator of Transistor Connectivity to Symbolic Cell Layout , 1984, ESSCIRC '84: Tenth European Solid-State Circuits Conference.

[16]  Takashi Satoh,et al.  A high packing density module generator for CMOS logic cells , 1988, DAC '88.

[17]  Daniel Gajski,et al.  LES: A Layout Expert System , 1987, 24th ACM/IEEE Design Automation Conference.

[18]  Viraphol Chaiyakul,et al.  Layout-area models for high-level synthesis , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[19]  Chak-Kuen Wong,et al.  On VHV-routing in channels with irregular boundaries , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Amnon Baron Cohen,et al.  Track assignment in the Pathway datapath layout assembler , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[21]  T. H. Sloane,et al.  CMOS leaf-cell design using simulated annealing , 1992, [1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems.

[22]  Yu-Chin Hsu,et al.  An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[23]  Yoko Watanabe,et al.  Datapath generator based on gate-level symbolic layout , 1991, DAC '90.