Fault masking issue on a dependable processor using BIST under highly electromagnetic environment

While power converter and inverter circuits have been enhanced for higher switching speed, higher voltage and higher power density, there are arising problems relating to the effect of near-field noise due to high-current pulse, which can severely affect the operations of the controllers for power converters and the surrounding logic circuits as multi-bit transient faults. A scheme to construct highly reliable processors which measures the noise duration by built-in self test (BIST) and avoids its effect by clock mitigation was proposed in our previous work. However, in some cases, the upper bounds of the noise duration distribution are underestimated due to insufficient testing and fault masking, resulting in faulty operations. In this paper, we further investigate these underestimating situations and then propose a test method to overcome the problem. We use SPICE simulation to evaluate the effectiveness of the proposed scheme.

[1]  Masayuki Arai,et al.  A Highly Reliable Digital Current Control using an Adaptive Sampling Method , 2014 .

[2]  Milo M. K. Martin,et al.  SafetyNet: improving the availability of shared memory multiprocessors with global checkpoint/recovery , 2002, Proceedings 29th Annual International Symposium on Computer Architecture.

[3]  Kajihara Seiji.  High Field Reliability Using Built-In Self Test , 2012 .

[4]  John P. Hayes,et al.  Transient fault characterization in dynamic noisy environments , 2005, IEEE International Conference on Test, 2005..

[5]  G. Surya Prasad,et al.  EMC issues of radar receiver-a case study , 2002, Proceedings of the International Conference on Electromagnetic Interference and Compatibility (IEEE Cat. No.02TH8620).

[6]  Satoshi Fukumoto,et al.  Optimal checkpointing policies using the checkpointing density , 1992 .

[7]  Masayuki Arai,et al.  A Dependable Processor by Using Built-in Self Test to Tolerate Periodical Transient Faults under Highly Electromagnetic Environment , 2012, 2012 IEEE 18th Pacific Rim International Symposium on Dependable Computing.

[8]  Mehdi Baradaran Tahoori,et al.  A transient error tolerant self-timed asynchronous architecture , 2010, 2010 15th IEEE European Test Symposium.

[9]  Kotaro Shimamura,et al.  A Single-Chip Fail-Safe Microprocessor with Memory Data Comparison Feature , 2006, 2006 12th Pacific Rim International Symposium on Dependable Computing (PRDC'06).

[10]  Tipp Moseley,et al.  PLR: A Software Approach to Transient Fault Tolerance for Multicore Architectures , 2009, IEEE Transactions on Dependable and Secure Computing.

[11]  Yi Ma,et al.  Efficient Transient-Fault Tolerance for Multithreaded Processors Using Dual-Thread Execution , 2006, 2006 International Conference on Computer Design.

[12]  Takeshi Kataoka,et al.  A Cost-Effective Dependable Microcontroller Architecture with Instruction-Level Rollback for Soft Error Recovery , 2007, 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07).

[13]  Hiroyuki Ochi,et al.  Fault Tolerant Dynamic Reconfigurable Device Based on EDAC with Rollback , 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[14]  U. Drofenik,et al.  PWM Converter Power Density Barriers , 2007, 2007 Power Conversion Conference - Nagoya.

[15]  裕介 松永,et al.  An Acceleration of Soft Error Torelance Estimation Method for Sequential Circuits by Reducing the Number of States , 2010 .

[16]  Kewal K. Saluja,et al.  Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[17]  Sandip Kundu,et al.  A Built-In Self-Test Scheme for Soft Error Rate Characterization , 2008, 2008 14th IEEE International On-Line Testing Symposium.

[18]  Maya Gokhale,et al.  Dynamic reconfiguration for management of radiation-induced faults in FPGAs , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[19]  Masayuki Arai,et al.  Test Data Compression of 100x for Scan-Based BIST , 2006, 2006 IEEE International Test Conference.

[20]  Jakob Lechner,et al.  Low Latency Recovery from Transient Faults for Pipelined Processor Architectures , 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

[21]  Mohammad Ababneh,et al.  Design and simulation of a PV-grid connected system , 2015, Int. J. Comput. Sci. Eng..

[22]  Akio Toba,et al.  Quantitative Estimation of Conducted Emission from an Inverter System , 2008 .

[23]  Yuki Yoshikawa,et al.  Reliability and Performance Analysis of FPGA-Based Fault Tolerant System , 2009, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[24]  M. D. Giles,et al.  Process Technology Variation , 2011, IEEE Transactions on Electron Devices.

[25]  Hisao Kubota,et al.  EMI Prediction Method for SiC Inverter by Developing an Accurate Model of Power Device , 2014 .

[26]  Wen-Yan Yin.  On-chip EMC issue: the implementation of patterned ground shields for silicon devices , 2007, EMC 2007.

[27]  Masahiro Iida,et al.  Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration , 2010, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines.

[28]  C. B. White.  Critical EMC test issues needing early resolution , 2012, 2012 IEEE International Symposium on Electromagnetic Compatibility.

[29]  Kus Vaclav,et al.  EMC issues of power electronic converters , 2009, 2009 IEEE International Symposium on Electromagnetic Compatibility.

[30]  Satoshi Fukumoto,et al.  Hybrid BIST using partially rotational scan , 2001, Proceedings 10th Asian Test Symposium.

[31]  Herbert Reichl,et al.  EMC issues in cars with electric drives , 2003, 2003 IEEE Symposium on Electromagnetic Compatibility. Symposium Record (Cat. No.03CH37446).

[32]  Yoneda Tomohiro.  Increasing Dependability based on Asynchronous Computation , 2010 .

[33]  Keiji Wada,et al.  Analysis and evaluation of near field noise voltage on power electronics circuits , 2009, 2009 International Conference on Power Electronics and Drive Systems (PEDS).

[34]  Imai Masashi,et al.  An Approach to Dependable Chip Multiprocessors with Process Pair and Swap Mechanism , 2009 .

[35]  Albert Meixner,et al.  Argus: Low-Cost, Comprehensive Error Detection in Simple Cores , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[36]  Sotirios G. Ziavras,et al.  A multiprocessor-on-a-programmable-chip reconfigurable system for matrix operations with power-grid case studies , 2015, Int. J. Comput. Sci. Eng..

[37]  Todd M. Austin,et al.  DIVA: a reliable substrate for deep submicron microarchitecture design , 1999, MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture.

[38]  Jean-Roger K. Kuvedu-Libla.  Design limitations of powertrain electronics — Automotive EMC challenges , 2009, 2009 IEEE International Symposium on Electromagnetic Compatibility.

[39]  Chris Eaglen.  EMC issues in advanced signalling, transmission based train control systems , 2006 .