Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs : Analytical model and design considerations

Abstract In this paper, we propose for the first time, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs. The impact of (i) lateral source/drain doping gradient ( d ), (ii) spacer width ( s ), (iii) spacer to doping gradient ratio ( s / d ) and (iv) silicon film thickness ( T si ), on short channel effects – threshold voltage ( V th ) and subthreshold slope ( S ), on-current ( I on ), off-current ( I off ) and I on / I off is extensively analysed by using the analytical model and 2D device simulations. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients and effective channel lengths. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimised to achieve high values of on-currents. The present work provides valuable design insights in the performance of nanoscale DG SOI devices with optimal source/drain engineering and serves as a tool to optimise important device and technological parameters for 65 nm technology node and below.

[1]  Umberto Ravaioli,et al.  Monte Carlo simulations of double-gate MOSFETs , 2003 .

[2]  Y. Omura,et al.  Engineering S/D diffusion for sub-100-nm channel SOI MOSFETs , 2004, IEEE Transactions on Electron Devices.

[3]  Wolfgang Rösner,et al.  Design considerations for fully depleted SOI transistors in the 25–50 nm gate length regime , 2003 .

[4]  T. Skotnicki,et al.  The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance , 2005, IEEE Circuits and Devices Magazine.

[5]  Yuan Taur,et al.  A 2-D analytical solution for SCEs in DG MOSFETs , 2004 .

[6]  V. Trivedi,et al.  Nanoscale FinFETs with gate-source/drain underlap , 2005, IEEE Transactions on Electron Devices.

[7]  Qiang Chen,et al.  A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs , 2002 .

[8]  Krishna C. Saraswat,et al.  Optimization of extrinsic source/drain resistance in ultrathin body double-gate FETs , 2003 .

[9]  Ching-Te Chuang,et al.  Process/physics-based threshold voltage model for nano-scaled double-gate devices , 2004 .

[10]  K. F. Lee,et al.  Scaling the Si MOSFET: from bulk to SOI to bulk , 1992 .

[11]  D. Frank,et al.  Generalized scale length for two-dimensional effects in MOSFETs , 1998, IEEE Electron Device Letters.

[12]  Y. Tosaka,et al.  Scaling theory for double-gate SOI MOSFET's , 1993 .

[13]  Abhinav Kranti,et al.  Analysis of quasi double gate method for performance prediction of deep submicron double gate SOI MOSFETs , 2005 .

[14]  T. Skotnicki,et al.  16 nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimisation , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[15]  A. Asenov.  Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFET's: A 3-D "atomistic" simulation study , 1998 .

[16]  E. Harrell,et al.  A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs , 2003 .

[17]  G. Alastair Armstrong,et al.  Parameter sensitivity for optimal design of 65 nm node double gate SOI transistors , 2005 .

[18]  J. Kavalieros,et al.  High performance fully-depleted tri-gate CMOS transistors , 2003, IEEE Electron Device Letters.

[19]  Abhinav Kranti,et al.  Performance assessment of nanoscale double- and triple-gate FinFETs , 2006 .

[20]  K. N. Ratnakumar,et al.  Short-channel MOST threshold voltage model , 1982 .

[21]  G. A. Armstrong,et al.  Device design considerations for nanoscale double and triple gate FinFETs , 2005, 2005 IEEE International SOI Conference Proceedings.

[22]  M. Lundstrom,et al.  Electron transport in a model Si transistor , 2000 .

[23]  S. Horiguchi,et al.  ELECTRONIC STRUCTURES AND PHONON-LIMITED ELECTRON MOBILITY OF DOUBLE-GATE SILICON-ON-INSULATOR SI INVERSION LAYERS , 1999 .

[24]  Abhinav Kranti,et al.  Design and optimization of thin film fully depleted vertical surrounding gate (VSG) MOSFETs for enhanced short channel immunity , 2002 .

[25]  F. Balestra,et al.  Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance , 1987, IEEE Electron Device Letters.

[26]  Abhinav Kranti,et al.  Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications , 2004 .