Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs

Multimedia applications usually have throughput constraints. An implementation must meet these constraints, while it minimizes resource usage and energy consumption. The compute intensive kernels of these applications are often specified as synchronous dataflow graphs. Communication between nodes in these graphs requires storage space which influences throughput. We present exact techniques to chart the Pareto space of throughput and storage tradeoffs, which can be used to determine the minimal storage space needed to execute a graph under a given throughput constraint. The feasibility of the approach is demonstrated with a number of examples

[1]  Edward A. Lee Consistency in Dataflow Graphs , 1991, IEEE Trans. Parallel Distributed Syst..

[2]  Sander Stuijk,et al.  Minimising buffer requirements of synchronous dataflow graphs with model checking , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[3]  Twan Basten,et al.  Task-level timing models for guaranteed performance in multiprocessor networks-on-chip , 2003, CASES '03.

[4]  Soonhoi Ha,et al.  Efficient code synthesis from extended dataflow graphs for multimedia applications , 2002, DAC '02.

[5]  Edward A. Lee,et al.  Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing , 1989, IEEE Transactions on Computers.

[6]  Heinrich Meyr,et al.  Scheduling for optimum data memory compaction in block diagram oriented software synthesis , 1995, 1995 International Conference on Acoustics, Speech, and Signal Processing.

[7]  Guang R. Gao,et al.  Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks , 2002, J. VLSI Signal Process..

[8]  Sandeep K. Shukla,et al.  A model checking approach to evaluating system level dynamic power management policies for embedded systems , 2001, Sixth IEEE International High-Level Design Validation and Test Workshop.

[9]  Edward A. Lee,et al.  Synthesis of Embedded Software from Synchronous Dataflow Specifications , 1999, J. VLSI Signal Process..

[10]  Sander Stuijk,et al.  Throughput Analysis of Synchronous Data Flow Graphs , 2006, Sixth International Conference on Application of Concurrency to System Design (ACSD'06).

[11]  Praveen K. Murthy,et al.  Shared memory implementations of synchronous dataflow specifications , 2000, DATE '00.

[12]  Sander Stuijk,et al.  SDF^3: SDF For Free , 2006, Sixth International Conference on Application of Concurrency to System Design (ACSD'06).

[13]  Edward A. Lee,et al.  Scheduling dynamic dataflow graphs with bounded memory using the token flow model , 1993, 1993 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[14]  Joseph Sifakis,et al.  A Methodology for the Construction of Scheduled Systems , 2000, FTRTFT.

[15]  Rudy Lauwereins,et al.  Data memory minimisation for synchronous data flow graphs emulated on DSP-FPGA targets , 1997, DAC.

[16]  S.S. Bhattacharyya,et al.  Shared memory implementations of synchronous dataflow specifications , 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

[17]  Yu-Chin Hsu,et al.  A formal approach to the scheduling problem in high level synthesis , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Shuvra S. Bhattacharyya,et al.  Embedded Multiprocessors: Scheduling and Synchronization , 2000 .

[19]  Guang R. Gao,et al.  A novel framework of register allocation for software pipelining , 1993, POPL '93.

[20]  Edward A. Lee,et al.  Software Synthesis from Dataflow Graphs , 1996 .

[21]  Guang R. Gao,et al.  A novel framework for multi-rate scheduling in DSP applications , 1993, Proceedings of International Conference on Application Specific Array Processors (ASAP '93).

[22]  Gerard J. Holzmann,et al.  The SPIN Model Checker - primer and reference manual , 2003 .

[23]  Wang Yi,et al.  TIMES: A Tool for Schedulability Analysis and Code Generation of Real-Time Systems , 2003, FORMATS.